From patchwork Fri Oct 22 07:52:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C835C433FE for ; Fri, 22 Oct 2021 07:55:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 659F860FC3 for ; Fri, 22 Oct 2021 07:55:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232584AbhJVH5Q (ORCPT ); Fri, 22 Oct 2021 03:57:16 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17446 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232586AbhJVH44 (ORCPT ); Fri, 22 Oct 2021 03:56:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889280; x=1666425280; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mGXSulOcLd/+pEdw+DTE5v6o3xipo1H1wT+9aSReL8M=; b=OkIEw3lKSEKvDtXtKHYQdpF7MHRZto+L1nWWB2+gjRD9gBxzaeYxBIPc TmoUkP7D8J4tfIcLJtV0HWofXm3loFm+06h9f5cjYg41sbe4mud4gnXPh uI8AVGXiTNUdNp2HP0cShY/27ewgh+CFuCB/Wdgsni5p6FcCUTDn7pk1k K1e1Cx2q4AJ0KUN2hk2Ii+o+4S1YcC0EAp5Xt00Ds6GUslGjYvDaVMtR7 cmY7QYVi2EE9u4eSK22xKsw3uNSgic6ZV1vkjDH4WyshPGX4Y8g5Tu2yI 2oU3mrRvFR6vyHxba630lkmrVxmcY3aBd/k2+FgwsVIYbjFlvPkWXZ30/ A==; IronPort-SDR: Nz/rmn6Caqi6ikJ75pwzOgC07QYIe7d2MhtiXUsQ2z3co3d1tRDalwK8z/qE9HVTkgvhbtDYdh C3PwljrQp71yh0Z29fI7y715kZ8n7Aqm/j7B+rId3LaO+PDiWtpwTxB/4BFJe15s0UXWksaFkV 7pb+avWIhhLHFZ1tUDWSFmo4TsTDunh7JyTjQf/nh4omih9r9tCyfxFIhf7lHNesd41jmx/e2n TCD9Yk98kiwT8Q0ggXKM7oSLtgcgUFTmZEgsju8x4dRj5fVsZkuogcAQ8ZwAb8+HjR9IS9aQDa sd8PXoSZAI/C/OkOCbI538nV X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538127" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:38 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:35 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 15/21] ARM: dts: at91: sama7g5: add nodes for video capture Date: Fri, 22 Oct 2021 10:52:41 +0300 Message-ID: <20211022075247.518880-16-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC (csi2 demux controller). These nodes represent the top level of the video capture hardware pipeline and are directly connected in hardware. Signed-off-by: Eugen Hristev --- arch/arm/boot/dts/sama7g5.dtsi | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 6c58c151c6d9..a8dda38ff18b 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -203,6 +203,55 @@ sdmmc2: mmc@e120c000 { status = "disabled"; }; + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <12>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <12>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + pwm: pwm@e1604000 { compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; reg = <0xe1604000 0x4000>;