From patchwork Thu Nov 25 15:56:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 12639485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AAB4C433F5 for ; Thu, 25 Nov 2021 16:09:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356448AbhKYQM5 (ORCPT ); Thu, 25 Nov 2021 11:12:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349570AbhKYQKz (ORCPT ); Thu, 25 Nov 2021 11:10:55 -0500 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA81BC0619E1; Thu, 25 Nov 2021 07:56:56 -0800 (PST) Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:2581:f820:804e:edb9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id DD3911F464B5; Thu, 25 Nov 2021 15:56:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=collabora.com; s=mail; t=1637855815; bh=I6l0ieSYxLXJOwlHwddu1GA3tRwgCsYplMmSEx+E23E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L7Y7r5klZNI7Kqew3GX5PdJpjYrwR12EgWk8Wb59P05Is7YV/bBsYbxlvtfeU97bj YbSW3ClViwenJIdG4sk+vE4N/VzB+cPlRBxax4gLwE0IgpFtbWFrlleeSFtcLcb5EU ewhDMQolJgzejlq/o7ULVp5HVmEfUNP8z9/rA74npYYbm+aTkgs/vMLQUt0ksOI/Vk afEvpX8S1ba6c+GgBSGGQVwzNL0jrN2arF7ejfwzWJaub+tNqDpTn3LEZ3ScvWmfEz G9IiTAFxMMJgxtikyCaFTk2jk0ddqaydCDKrAzJHm4674sRJqKYhx4gFps+oDIg0Wx famyW2gMt34pQ== From: Benjamin Gaignard To: mchehab@kernel.org, ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, hverkuil-cisco@xs4all.nl Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-staging@lists.linux.dev, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v3 3/4] media: hantro: Use syscon instead of 'ctrl' register Date: Thu, 25 Nov 2021 16:56:49 +0100 Message-Id: <20211125155650.630977-4-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211125155650.630977-1-benjamin.gaignard@collabora.com> References: <20211125155650.630977-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org In order to be able to share the control hardware block between VPUs use a syscon instead a ioremap it in the driver. To keep the compatibility with older DT if 'nxp,imx8mq-vpu-ctrl' phandle is not found look at 'ctrl' reg-name. With the method it becomes useless to provide a list of register names so remove it. Signed-off-by: Benjamin Gaignard Reviewed-by: Philipp Zabel Please note that the only purpose of this commit is to allow to test G2 hardware block for IMX8MQ until a proper solution isuing power domain can be found. Do not merge it. --- drivers/staging/media/hantro/hantro.h | 5 ++- drivers/staging/media/hantro/imx8m_vpu_hw.c | 48 +++++++++++++-------- 2 files changed, 34 insertions(+), 19 deletions(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index 7da23f7f207a..616b5a6854cd 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -13,6 +13,7 @@ #define HANTRO_H_ #include +#include #include #include #include @@ -174,7 +175,7 @@ hantro_vdev_to_func(struct video_device *vdev) * @reg_bases: Mapped addresses of VPU registers. * @enc_base: Mapped address of VPU encoder register for convenience. * @dec_base: Mapped address of VPU decoder register for convenience. - * @ctrl_base: Mapped address of VPU control block. + * @ctrl_base: Regmap of VPU control block. * @vpu_mutex: Mutex to synchronize V4L2 calls. * @irqlock: Spinlock to synchronize access to data structures * shared with interrupt handlers. @@ -193,7 +194,7 @@ struct hantro_dev { void __iomem **reg_bases; void __iomem *enc_base; void __iomem *dec_base; - void __iomem *ctrl_base; + struct regmap *ctrl_base; struct mutex vpu_mutex; /* video_device lock */ spinlock_t irqlock; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index 1a43f6fceef9..d7a63b41eb0e 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -7,6 +7,7 @@ #include #include +#include #include "hantro.h" #include "hantro_jpeg.h" @@ -25,30 +26,28 @@ #define CTRL_G1_PP_FUSE 0x0c #define CTRL_G2_DEC_FUSE 0x10 +static const struct regmap_config ctrl_regmap_ctrl = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 0x14, +}; + static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) { - u32 val; - /* Assert */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val &= ~reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); + regmap_update_bits(vpu->ctrl_base, CTRL_SOFT_RESET, reset_bits, 0); udelay(2); /* Release */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val |= reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); + regmap_update_bits(vpu->ctrl_base, CTRL_SOFT_RESET, + reset_bits, reset_bits); } static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) { - u32 val; - - val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); - val |= clock_bits; - writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); + regmap_update_bits(vpu->ctrl_base, CTRL_CLOCK_ENABLE, + clock_bits, clock_bits); } static int imx8mq_runtime_resume(struct hantro_dev *vpu) @@ -65,9 +64,9 @@ static int imx8mq_runtime_resume(struct hantro_dev *vpu) imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2); /* Set values of the fuse registers */ - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); + regmap_write(vpu->ctrl_base, CTRL_G1_DEC_FUSE, 0xffffffff); + regmap_write(vpu->ctrl_base, CTRL_G1_PP_FUSE, 0xffffffff); + regmap_write(vpu->ctrl_base, CTRL_G2_DEC_FUSE, 0xffffffff); clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); @@ -211,7 +210,22 @@ static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id) static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) { - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; + struct device_node *np = vpu->dev->of_node; + + vpu->ctrl_base = syscon_regmap_lookup_by_phandle(np, "nxp,imx8m-vpu-ctrl"); + if (IS_ERR(vpu->ctrl_base)) { + struct resource *res; + void __iomem *ctrl; + + res = platform_get_resource_byname(vpu->pdev, IORESOURCE_MEM, "ctrl"); + ctrl = devm_ioremap_resource(vpu->dev, res); + if (IS_ERR(ctrl)) + return PTR_ERR(ctrl); + + vpu->ctrl_base = devm_regmap_init_mmio(vpu->dev, ctrl, &ctrl_regmap_ctrl); + if (IS_ERR(vpu->ctrl_base)) + return PTR_ERR(vpu->ctrl_base); + } return 0; }