| Message ID | 20211208120744.2415-6-dafna.hirschfeld@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | iommu/mediatek: Fix tlb flush logic | expand |
Il 08/12/21 13:07, Dafna Hirschfeld ha scritto: > From: Yong Wu <yong.wu@mediatek.com> > > Prepare for 2 HWs that sharing pgtable in different power-domains. > > When there are 2 M4U HWs, it may has problem in the flush_range in which > we get the pm_status via the m4u dev, BUT that function don't reflect the > real power-domain status of the HW since there may be other HW also use > that power-domain. > > DAM allocation is often done while the allocating device is runtime > suspended. In such a case the iommu will also be suspended and partial > flushing of the tlb will not be executed. > Therefore, we add a tlb_flush_all in the pm_runtime_resume to make > sure the tlb is always clean. > > In other case, the iommu's power should be active via device > link with smi. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > [move the call to mtk_iommu_tlb_flush_all to the bottom of resume cb, improve doc/log] > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 195a411e3087..4799cd06511b 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -997,6 +997,13 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); + + /* + * Users may allocate dma buffer before they call pm_runtime_get, + * in which case it will lack the necessary tlb flush. + * Thus, make sure to update the tlb after each PM resume. + */ + mtk_iommu_tlb_flush_all(data); return 0; }