From patchwork Wed Jan 5 09:37:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 12704174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2218C433F5 for ; Wed, 5 Jan 2022 09:38:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238945AbiAEJiL (ORCPT ); Wed, 5 Jan 2022 04:38:11 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:43172 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238925AbiAEJiI (ORCPT ); Wed, 5 Jan 2022 04:38:08 -0500 X-UUID: 0b62cb6761a14b16ad67fc6ca200066e-20220105 X-UUID: 0b62cb6761a14b16ad67fc6ca200066e-20220105 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 779097632; Wed, 05 Jan 2022 17:38:01 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 Jan 2022 17:38:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 5 Jan 2022 17:38:00 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Hans Verkuil , Jernej Skrabec CC: Chun-Kuang Hu , Geert Uytterhoeven , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , AngeloGioacchino Del Regno , Maoguang Meng , daoyuan huang , Ping-Hsun Wu , , , , , , , , , Subject: [PATCH v11 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Date: Wed, 5 Jan 2022 17:37:56 +0800 Message-ID: <20220105093758.6850-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220105093758.6850-1-moudy.ho@mediatek.com> References: <20220105093758.6850-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds DT binding document for Media Data Path 3 (MDP3) a unit in multimedia system used for scaling and color format convert. Signed-off-by: Moudy Ho --- .../bindings/media/mediatek,mdp3-rdma.yaml | 193 ++++++++++++++++++ .../bindings/media/mediatek,mdp3-rsz.yaml | 55 +++++ .../bindings/media/mediatek,mdp3-wrot.yaml | 57 ++++++ .../bindings/soc/mediatek/mediatek,ccorr.yaml | 47 +++++ .../bindings/soc/mediatek/mediatek,wdma.yaml | 58 ++++++ 5 files changed, 410 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml new file mode 100644 index 000000000000..002503383934 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Read Direct Memory Access + +maintainers: + - Matthias Brugger + +description: | + Mediatek Read Direct Memory Access(RDMA) component used to do read DMA. + It contains one line buffer to store the sufficient pixel data, and + must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml + for details. + The 1st RDMA is also used to be a controller node in Media Data Path 3(MDP3) + that containing MMSYS, MUTEX, GCE and SCP settings. + +properties: + compatible: + oneOf: + - items: + # MDP3 controller node + - const: mediatek,mt8183-mdp3 + - const: mediatek,mt8183-mdp3-rdma0 + - items: + # normal RDMA conponent + - const: mediatek,mt8183-mdp3-rdma0 + + mediatek,scp: + description: The node of system control processor (SCP), using + the remoteproc & rpmsg framework. + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + + mediatek,mdp3-comps: + description: MTK sub-system of direct-link or DIP + $ref: /schemas/types.yaml#/definitions/string-array + items: + - enum: + # MDP direct-link input path selection, create a + # component for path connectedness of HW pipe control + - mediatek,mt8183-mdp3-dl1 + - enum: + - mediatek,mt8183-mdp3-dl2 + - enum: + # MDP direct-link output path selection, create a + # component for path connectedness of HW pipe control + - mediatek,mt8183-mdp3-path1 + - enum: + - mediatek,mt8183-mdp3-path2 + - enum: + # Input DMA of ISP PASS2 (DIP) module for raw image input + - mediatek,mt8183-mdp3-imgi + - enum: + # Output DMA of ISP PASS2 (DIP) module for YUV image output + - mediatek,mt8183-mdp3-exto + + reg: + items: + - description: basic RDMA HW address + - description: MDP direct-link 1st and 2nd input + - description: MDP direct-link 1st output + - description: MDP direct-link 2nd output + - description: ISP input and output + + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: GCE client for RDMA + - description: GCR client for MDP direct-link 1st and 2nd input + - description: GCR client for MDP direct-link 1st output + - description: GCR client for MDP direct-link 2nd output + - description: GCR client for ISP input and output + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA clock + - description: RSZ clock + - description: direck-link TX clock in MDP side + - description: direck-link RX clock in MDP side + - description: direck-link TX clock in ISP side + - description: direck-link RX clock in ISP side + + iommus: + maxItems: 1 + + mediatek,mmsys: + description: The node of mux(multiplexer) controller for HW connections. + $ref: /schemas/types.yaml#/definitions/phandle + + mediatek,mm-mutex: + description: The node of sof(start of frame) signal controller. + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + + mediatek,mailbox-gce: + description: The node of global command engine (GCE), used to read/write + registers with critical time limitation. + $ref: /schemas/types.yaml#/definitions/phandle + + mboxes: + items: + - description: used for 1st data pipe from RDMA + - description: used for 2nd data pipe from RDMA + - description: used for 3rd data pipe from Direct-Link + - description: used for 4th data pipe from Direct-Link + + gce-subsys: + description: sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/types.yaml#/definitions/phandle-array + +if: + properties: + compatible: + contains: + const: mediatek,mt8183-mdp3 + +then: + required: + - mediatek,scp + - mediatek,mmsys + - mediatek,mm-mutex + - mediatek,mailbox-gce + - mboxes + - gce-subsys + +required: + - compatible + - reg + - clocks + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + mdp3_rdma0: mdp3_rdma0@14001000 { + compatible = "mediatek,mt8183-mdp3", + "mediatek,mt8183-mdp3-rdma0"; + mediatek,scp = <&scp>; + mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1", + "mediatek,mt8183-mdp3-dl2", + "mediatek,mt8183-mdp3-path1", + "mediatek,mt8183-mdp3-path2", + "mediatek,mt8183-mdp3-imgi", + "mediatek,mt8183-mdp3-exto"; + reg = <0x14001000 0x1000>, + <0x14000000 0x1000>, + <0x14005000 0x1000>, + <0x14006000 0x1000>, + <0x15020000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>, + <&gce SUBSYS_1400XXXX 0 0x1000>, + <&gce SUBSYS_1400XXXX 0x5000 0x1000>, + <&gce SUBSYS_1400XXXX 0x6000 0x1000>, + <&gce SUBSYS_1502XXXX 0 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>, + <&mmsys CLK_MM_MDP_DL_TXCK>, + <&mmsys CLK_MM_MDP_DL_RX>, + <&mmsys CLK_MM_IPU_DL_TXCK>, + <&mmsys CLK_MM_IPU_DL_RX>; + iommus = <&iommu>; + mediatek,mmsys = <&mmsys>; + mediatek,mm-mutex = <&mutex>; + mediatek,mailbox-gce = <&gce>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, + <&gce 21 CMDQ_THR_PRIO_LOWEST>, + <&gce 22 CMDQ_THR_PRIO_LOWEST>, + <&gce 23 CMDQ_THR_PRIO_LOWEST>; + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, + <&gce 0x14010000 SUBSYS_1401XXXX>, + <&gce 0x14020000 SUBSYS_1402XXXX>, + <&gce 0x15020000 SUBSYS_1502XXXX>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml new file mode 100644 index 000000000000..cd4cf1531535 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Resizer + +maintainers: + - Matthias Brugger + +description: | + One of Media Data Path 3 (MDP3) components used to do frame resizing. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-rsz0 + - mediatek,mt8183-mdp3-rsz1 + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + clocks: + minItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_rsz0: mdp3_rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz0"; + reg = <0x14003000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3_rsz1: mdp3_rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz1"; + reg = <0x14004000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml new file mode 100644 index 000000000000..7b0f9c4fffd7 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Write DMA with Rotation + +maintainers: + - Matthias Brugger + +description: | + One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-wrot0 + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + minItems: 1 + + iommus: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + mdp3_wrot0: mdp3_wrot0@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot0"; + reg = <0x14005000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu>; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml new file mode 100644 index 000000000000..cf23f4f5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek color correction + +maintainers: + - Matthias Brugger + +description: | + Mediatek color correction with 3X3 matrix. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-ccorr + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + clocks: + minItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_ccorr: mdp3_ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + reg = <0x1401c000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml new file mode 100644 index 000000000000..4057b5232e45 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Write Direct Memory Access + +maintainers: + - Matthias Brugger + +description: | + Mediatek Write Direct Memory Access(WDMA) component used to write + the data into DMA. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-wdma + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + minItems: 1 + + iommus: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + mdp3_wdma: mdp3_wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + reg = <0x14006000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu>; + };