From patchwork Wed Jan 5 09:37:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 12704172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F61C433FE for ; Wed, 5 Jan 2022 09:38:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238933AbiAEJiI (ORCPT ); Wed, 5 Jan 2022 04:38:08 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:44540 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233853AbiAEJiF (ORCPT ); Wed, 5 Jan 2022 04:38:05 -0500 X-UUID: f136ce1af7864752ad8970b3f3126001-20220105 X-UUID: f136ce1af7864752ad8970b3f3126001-20220105 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1809775565; Wed, 05 Jan 2022 17:38:01 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 Jan 2022 17:38:01 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 Jan 2022 17:38:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 5 Jan 2022 17:38:00 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Hans Verkuil , Jernej Skrabec CC: Chun-Kuang Hu , Geert Uytterhoeven , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , AngeloGioacchino Del Regno , Maoguang Meng , daoyuan huang , Ping-Hsun Wu , , , , , , , , , Subject: [PATCH v11 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes Date: Wed, 5 Jan 2022 17:37:57 +0800 Message-ID: <20220105093758.6850-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220105093758.6850-1-moudy.ho@mediatek.com> References: <20220105093758.6850-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108 ++++++++++++++++++++++- 1 file changed, 107 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index ba4584faca5a..b872ef1ff6b3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1325,6 +1325,79 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + mdp3_rdma0: mdp3_rdma0@14001000 { + compatible = "mediatek,mt8183-mdp3", + "mediatek,mt8183-mdp3-rdma0"; + mediatek,scp = <&scp>; + mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1", + "mediatek,mt8183-mdp3-dl2", + "mediatek,mt8183-mdp3-path1", + "mediatek,mt8183-mdp3-path2", + "mediatek,mt8183-mdp3-imgi", + "mediatek,mt8183-mdp3-exto"; + reg = <0 0x14001000 0 0x1000>, + <0 0x14000000 0 0x1000>, + <0 0x14005000 0 0x1000>, + <0 0x14006000 0 0x1000>, + <0 0x15020000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>, + <&gce SUBSYS_1400XXXX 0 0x1000>, + <&gce SUBSYS_1400XXXX 0x5000 0x1000>, + <&gce SUBSYS_1400XXXX 0x6000 0x1000>, + <&gce SUBSYS_1502XXXX 0 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>, + <&mmsys CLK_MM_MDP_DL_TXCK>, + <&mmsys CLK_MM_MDP_DL_RX>, + <&mmsys CLK_MM_IPU_DL_TXCK>, + <&mmsys CLK_MM_IPU_DL_RX>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,mmsys = <&mmsys>; + mediatek,mm-mutex = <&mutex>; + mediatek,mailbox-gce = <&gce>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST>, + <&gce 22 CMDQ_THR_PRIO_LOWEST>, + <&gce 23 CMDQ_THR_PRIO_LOWEST>; + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, + <&gce 0x14010000 SUBSYS_1401XXXX>, + <&gce 0x14020000 SUBSYS_1402XXXX>, + <&gce 0x15020000 SUBSYS_1502XXXX>; + }; + + mdp3_rsz0: mdp3_rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz0"; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3_rsz1: mdp3_rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz1"; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp3_wrot0: mdp3_wrot0@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot0"; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp3_wdma: mdp3_wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu M4U_PORT_MDP_WDMA0>; + }; + ovl0: ovl@14008000 { compatible = "mediatek,mt8183-disp-ovl"; reg = <0 0x14008000 0 0x1000>; @@ -1449,7 +1522,33 @@ interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; mediatek,gce-events = , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; larb0: larb@14017000 { @@ -1473,6 +1572,13 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; }; + mdp3_ccorr: mdp3_ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + reg = <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>;