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[31.178.191.245]) by smtp.gmail.com with ESMTPSA id a22sm491184lfr.24.2022.02.14.13.29.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Feb 2022 13:29:11 -0800 (PST) From: Piotr Oniszczuk To: linux-media@vger.kernel.org, Linux-rockchip@lists.infradead.org Cc: Piotr Oniszczuk Subject: [PATCH v2 2/3] arm64: dts: rockchip: Add VPU support for RK3568/RK3566 Date: Mon, 14 Feb 2022 22:29:54 +0100 Message-Id: <20220214212955.1178947-2-piotr.oniszczuk@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20220214212955.1178947-1-piotr.oniszczuk@gmail.com> References: <20220214212955.1178947-1-piotr.oniszczuk@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Piotr Oniszczuk RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8 video formats. This patch enables RK356x video decoder in RK356x device-tree include. Tested on [1] with FFmpeg v4l2_request code taken from [2] with MPEG2, H.642 and VP8 samples with results [3]. [1] https://github.com/warpme/minimyth2 [2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch [3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt Signed-off-by: Piotr Oniszczuk Reviewed-by: Ezequiel Garcia --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index a68033a23975..33ecaafa8cb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -390,6 +390,26 @@ power-domain@RK3568_PD_RKVENC { }; }; + vpu: video-codec@fdea0400 { + compatible = "rockchip,rk3568-vpu"; + reg = <0x0 0xfdea0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vdpu_mmu>; + power-domains = <&power RK3568_PD_VPU>; + }; + + vdpu_mmu: iommu@fdea0800 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdea0800 0x0 0x40>; + interrupts = ; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + power-domains = <&power RK3568_PD_VPU>; + #iommu-cells = <0>; + }; + sdmmc2: mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>;