diff mbox series

[5/7] v4l: vsp1: Add safety mechanism registers

Message ID 20220629105135.2652773-6-kieran.bingham+renesas@ideasonboard.com (mailing list archive)
State New, archived
Headers show
Series renesas: vsp1: debugfs facility | expand

Commit Message

Kieran Bingham June 29, 2022, 10:51 a.m. UTC 
Provide the Safety Mechanism registers so that they can be reported
through debugfs

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
 .../media/platform/renesas/vsp1/vsp1_debugfs.c |  6 ++++++
 .../media/platform/renesas/vsp1/vsp1_regs.h    | 18 ++++++++++++++++++
 2 files changed, 24 insertions(+)
diff mbox series

Patch

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c b/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c
index 3bae9556f38b..0340acd3209b 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c
@@ -121,6 +121,12 @@  static const struct debugfs_reg32 vsp1_regset[] = {
 	VSP1_DBFS_REG(VI6_MRESET_ENB1),
 	VSP1_DBFS_REG(VI6_MRESET),
 
+	VSP1_DBFS_REG(VI6_WPF0_WDT),
+	VSP1_DBFS_REG(VI6_WPF0_FRCNT),
+	VSP1_DBFS_REG(VI6_ECM0_IRQ_ENB),
+	VSP1_DBFS_REG(VI6_ECM0_IRQ_STA),
+	VSP1_DBFS_REG(VI6_CTL_ERRINJ),
+
 	VSP1_DBFS_REG_DECODE(VI6_STATUS, decode_vi6_status),
 
 	VSP1_DBFS_REG_DECODE(VI6_WPF_IRQ_ENB(0), decode_vi6_wpf_enb),
diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 86855b34dcaf..f90a01a21b06 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -70,6 +70,24 @@ 
 #define VI6_WPF_LINE_COUNT(n)		(0x0084 + (n) * 4)
 #define VI6_WPF_LINE_COUNT_MASK		(0x1fffff << 0)
 
+/* Safety Mechanism */
+#define VI6_WPF0_WDT			0x00c4
+#define VI6_WPF0_WDT_WDTEN		BIT(16)
+#define VI6_WPF0_TIMER_CYC_MASK		(0xffff << 0)
+
+#define VI6_WPF0_FRCNT			0x00d4
+#define VI6_WPF0_FRCNT_MASK		(0xfff << 0)
+
+#define VI6_ECM0_IRQ_ENB		0x00dc
+#define VI6_ECM0_IRQ_ENB_W0ALME		BIT(24)
+#define VI6_ECM0_IRQ_ENB_RRSP0E		BIT(0)
+
+#define VI6_ECM0_IRQ_STA		0x00e0
+#define VI6_ECM0_IRQ_STA_W0ALM		BIT(24)
+#define VI6_ECM0_IRQ_STA_RRSP0		BIT(0)
+
+#define VI6_CTL_ERRINJ			0x00e8
+
 /* -----------------------------------------------------------------------------
  * Display List Control Registers
  */