From patchwork Thu Aug 18 20:33:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Dufresne X-Patchwork-Id: 12947857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC1FCC28B2B for ; Thu, 18 Aug 2022 20:34:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346104AbiHRUeE (ORCPT ); Thu, 18 Aug 2022 16:34:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346103AbiHRUeC (ORCPT ); Thu, 18 Aug 2022 16:34:02 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FA1F3F1E2; Thu, 18 Aug 2022 13:34:00 -0700 (PDT) Received: from whitebuilder.lan (192-222-136-102.qc.cable.ebox.net [192.222.136.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nicolas) by madras.collabora.co.uk (Postfix) with ESMTPSA id 606AE6601BCA; Thu, 18 Aug 2022 21:33:57 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1660854839; bh=GgPaajQKLXv1616Hqx0PaERx4rlMxlMQza9pzPITvMk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JYDZhzavP0trr+jEEMho+vU+B85/kDtbonYhDioXoPlFOh/TXFSNbC08MUU+JTXQc HSaIkIYCz6PG8Ab++c23BV+/fPUBLzM8FSyaxqBHSVBJRnvf/+QDfW3Y5zQza7TlvO +3HPLFDWffWf5GTbgqED4lOZEfVTuSgVHUcVoVHBBlcYIqeR2jq/ky7b8W1X6SrFnY oz6Fc087flGK0HZ0J2xWb1KjOd1N5XaR1mnAY4y9jFq+N7ylsDPIriVrZV4eCwwmtq Dx71wDW//MViP5NhPmjnZ2qCcPrifKhCxa9vmOBcDSY+5X7FnLP5KGosaC+0r02iMC qEeno4yLzr6Cg== From: Nicolas Dufresne To: linux-media@vger.kernel.org, Maxime Ripard , Paul Kocialkowski , Mauro Carvalho Chehab , Greg Kroah-Hartman , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: kernel@collabora.com, Dmitry Osipenko , stable@vger.kernel.org, Nicolas Dufresne , linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/3] media: cedrus: Fix endless loop in cedrus_h265_skip_bits() Date: Thu, 18 Aug 2022 16:33:08 -0400 Message-Id: <20220818203308.439043-4-nicolas.dufresne@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220818203308.439043-1-nicolas.dufresne@collabora.com> References: <20220818203308.439043-1-nicolas.dufresne@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Dmitry Osipenko The busy status bit may never de-assert if number of programmed skip bits is incorrect, resulting in a kernel hang because the bit is polled endlessly in the code. Fix it by adding timeout for the bit-polling. This problem is reproducible by setting the data_bit_offset field of the HEVC slice params to a wrong value by userspace. Cc: stable@vger.kernel.org Reported-by: Nicolas Dufresne Signed-off-by: Dmitry Osipenko Signed-off-by: Nicolas Dufresne --- drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index f703c585d91c5..f0bc118021b0a 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -227,6 +227,7 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) { int count = 0; + u32 reg; while (count < num) { int tmp = min(num - count, 32); @@ -234,8 +235,9 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_FLUSH_BITS | VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp)); - while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY) - udelay(1); + + if (cedrus_wait_for(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_VLD_BUSY)) + dev_err_ratelimited(dev->dev, "timed out waiting to skip bits\n"); count += tmp; }