From patchwork Mon Jan 16 03:21:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 13102519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6769C677F1 for ; Mon, 16 Jan 2023 03:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231869AbjAPDWP (ORCPT ); Sun, 15 Jan 2023 22:22:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231812AbjAPDWE (ORCPT ); Sun, 15 Jan 2023 22:22:04 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 831C97AAC; Sun, 15 Jan 2023 19:22:00 -0800 (PST) X-UUID: ea7b2e68954c11ed945fc101203acc17-20230116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=aY4CAf3skfHLYZ3AYMyo1tLHqy+vDAlxRtPewRLh9GA=; b=tpcvH43fXVoOflC515ZfTF8ZkpKiNDqK1v2jQlfrvSMSBf+d65hHd1RubwywEgfgyDeb3t0j/y6WSzYlx2AzRWrCFIz/J3zT90q4oA5gMldyjnlZIo8+YwSyIWhHNo+KrI6AnLXn0bdqnmQVGNJ0EvTOXsHYiXG9V4qlr1X7S+I=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17,REQID:a6c693e6-d600-442a-ad45-cb5e45f44902,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:543e81c,CLOUDID:e1f7ba54-dd49-462e-a4be-2143a3ddc739,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: ea7b2e68954c11ed945fc101203acc17-20230116 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 248105765; Mon, 16 Jan 2023 11:21:50 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 16 Jan 2023 11:21:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 16 Jan 2023 11:21:49 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [RESEND v3 08/13] media: platform: mtk-mdp3: extend GCE event waiting in RDMA and WROT Date: Mon, 16 Jan 2023 11:21:42 +0800 Message-ID: <20230116032147.23607-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230116032147.23607-1-moudy.ho@mediatek.com> References: <20230116032147.23607-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Support for multiple RDMA/WROT waits for GCE events. Signed-off-by: Moudy Ho --- .../mediatek/mdp3/mt8183/mdp3-plat-mt8183.h | 2 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 17 +++++++++++------ .../platform/mediatek/mdp3/mtk-mdp3-core.h | 2 ++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h index 6dd06131e256..35425299e9bd 100644 --- a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h +++ b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h @@ -11,8 +11,10 @@ static const struct mdp_platform_config mt8183_plat_cfg = { .rdma_support_10bit = true, .rdma_rsz1_sram_sharing = true, .rdma_upsample_repeat_only = true, + .rdma_event_num = 1, .rsz_disable_dcm_small_sample = false, .wrot_filter_constraint = false, + .wrot_event_num = 1, }; static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 576b90a2fb9d..9b1b7fbb3d6b 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -280,14 +280,17 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) { + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); struct device *dev = &ctx->comp->mdp_dev->pdev->dev; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (ctx->comp->alias_id == 0) + if (ctx->comp->alias_id < mdp_cfg->rdma_event_num) { MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); - else - dev_err(dev, "Do not support RDMA1_DONE event\n"); + } else { + dev_err(dev, "Invalid RDMA event %d\n", ctx->comp->alias_id); + return -EINVAL; + } /* Disable RDMA */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); @@ -582,10 +585,12 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (ctx->comp->alias_id == 0) + if (ctx->comp->alias_id < mdp_cfg->wrot_event_num) { MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); - else - dev_err(dev, "Do not support WROT1_DONE event\n"); + } else { + dev_err(dev, "Invalid WROT event %d!\n", ctx->comp->alias_id); + return -EINVAL; + } if (mdp_cfg && mdp_cfg->wrot_filter_constraint) MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index e3e60b106c72..a9beb8bd440b 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -40,8 +40,10 @@ struct mdp_platform_config { bool rdma_support_10bit; bool rdma_rsz1_sram_sharing; bool rdma_upsample_repeat_only; + u32 rdma_event_num; bool rsz_disable_dcm_small_sample; bool wrot_filter_constraint; + u32 wrot_event_num; }; /* indicate which mutex is used by each pipepline */