From patchwork Mon Apr 3 09:13:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 13197835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8605BC76196 for ; Mon, 3 Apr 2023 09:15:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231895AbjDCJPf (ORCPT ); Mon, 3 Apr 2023 05:15:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231555AbjDCJP3 (ORCPT ); Mon, 3 Apr 2023 05:15:29 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2625F764; Mon, 3 Apr 2023 02:15:09 -0700 (PDT) X-UUID: 04740214d20011edb6b9f13eb10bd0fe-20230403 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lpfNQKTfP2YyAAu6CpD43JhcPlq1HIOIhM6xNel8+1I=; b=J/IdTEYt/QIr7AAUxY/x7Ir4Z5fE/KkPp+QUzN2PVVAgf80AjHkSuEMD1msdunphO+zzvwZLMZYeOs2QwNW5cb5fPeS5mLu+QGDPZTM8gLDlH/x+uw3OjXSzFLU+7EGgOg6oxGCFViKbKnpmjDq85J1MH7HNJTmhhOvJ/zRMSKU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:b52e8eeb-9c44-4051-a0d9-18915da540db,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:120426c,CLOUDID:c8d823b5-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 04740214d20011edb6b9f13eb10bd0fe-20230403 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 292261250; Mon, 03 Apr 2023 17:15:03 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 3 Apr 2023 17:15:02 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 3 Apr 2023 17:15:01 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Mauro Carvalho Chehab , Rob Herring CC: Will Deacon , Robin Murphy , Krzysztof Kozlowski , Hans Verkuil , , , , , , , , "AngeloGioacchino Del Regno" , , , , Yunfei Dong , kyrie wu , , , , Yong Wu Subject: [PATCH v6 05/14] iommu/mediatek: mt8192: Add iova_region_larb_msk Date: Mon, 3 Apr 2023 17:13:28 +0800 Message-ID: <20230403091337.26745-6-yong.wu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230403091337.26745-1-yong.wu@mediatek.com> References: <20230403091337.26745-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add iova_region_larb_msk for mt8192. We separate the 16GB iova regions by each device's larbid/portid. Note: larb3/6/8/10/12/15 connect nothing in this SoC. Refer to the comment in include/dt-bindings/memory/mt8192-larb-port.h Define a new macro MT8192_MULTI_REGION_NR_MAX to indicate the index of mt8xxx_larb_region_msk and "struct mtk_iommu_iova_region mt8192_multi_dom" are the same. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index bc936709fbe6..672059f9e0b7 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -336,7 +336,12 @@ static const struct mtk_iommu_iova_region single_domain[] = { {.iova_base = 0, .size = SZ_4G}, }; -static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { +#define MT8192_MULTI_REGION_NR_MAX 6 + +#define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \ + MT8192_MULTI_REGION_NR_MAX : 1) + +static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = { { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */ @@ -1534,6 +1539,17 @@ static const struct mtk_iommu_plat_data mt8186_data_mm = { .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), }; +static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { + [0] = {~0, ~0}, /* Region0: larb0/1 */ + [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */ + [2] = {0, 0, ~0, 0, 0, 0, 0, 0, /* Region2: larb2/9/11/13/14/16/17/18/19/20 */ + 0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0, + ~0, ~0, ~0, ~0, ~0}, + [3] = {0}, + [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ + [5] = {[14] = BIT(4) | BIT(5)}, /* larb14 port4/5 */ +}; + static const struct mtk_iommu_plat_data mt8192_data = { .m4u_plat = M4U_MT8192, .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | @@ -1543,6 +1559,7 @@ static const struct mtk_iommu_plat_data mt8192_data = { .banks_enable = {true}, .iova_region = mt8192_multi_dom, .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), + .iova_region_larb_msk = mt8192_larb_region_msk, .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, {0, 14, 16}, {0, 13, 18, 17}}, };