From patchwork Fri Sep 29 14:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 13404384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 273CAE71D43 for ; Fri, 29 Sep 2023 14:31:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233581AbjI2Obc (ORCPT ); Fri, 29 Sep 2023 10:31:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233446AbjI2ObV (ORCPT ); Fri, 29 Sep 2023 10:31:21 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C18A1AE; Fri, 29 Sep 2023 07:31:18 -0700 (PDT) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38TATqi4029805; Fri, 29 Sep 2023 16:30:38 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=WpHnGZEPjkA8pCPTOt8EGauEpCnanOA8eKhZUu2oK08=; b=Do qaWG4yL0stjibP6OYzD81kWKzvjDw6sMRzMre4VluJj0nsnCEwge1BfGAPdEsAIy SB57gw90fTZvIHAJPucSGD2BSmhK4bUVjR5IlskMLRwjoDTvKHGF2JSC0xxYSlpG +kIzCDHysEX5ajTQ8qT2hW18bg0Rm5WMsJX9wMrWAZ8aw0/UOaCK9yMfdzcWcIJA gU6IA6B+LOw3XLyBAMOk9yldMJA3O5gmBjvS8q8dGEsJgUPowpunXJhW4jHFbrVc Pqol12OM33zSqI87Af3TY6xCYe2OwyIHaXpGWNxSWP8TdW08RfvPO6YcdNA0/5gs pAHf11d+D4AWzwMMqWGQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3tcq63h6m6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 29 Sep 2023 16:30:38 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5E502100057; Fri, 29 Sep 2023 16:30:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 51D6E25AF10; Fri, 29 Sep 2023 16:30:37 +0200 (CEST) Received: from localhost (10.201.20.32) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 29 Sep 2023 16:30:36 +0200 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v5 03/11] dt-bindings: bus: document RIFSC Date: Fri, 29 Sep 2023 16:28:44 +0200 Message-ID: <20230929142852.578394-4-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230929142852.578394-1-gatien.chevallier@foss.st.com> References: <20230929142852.578394-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.32] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-29_13,2023-09-28_03,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources. Signed-off-by: Gatien Chevallier --- Changes in V5: - Renamed feature-domain* to access-control* Changes in V2: - Corrected errors highlighted by Rob's robot - No longer define the maxItems for the "feature-domains" property - Fix example (node name, status) - Declare "feature-domain-names" as an optional property for child nodes - Fix description of "feature-domains" property .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml new file mode 100644 index 000000000000..c28fceff3036 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation framework security controller + +maintainers: + - Gatien Chevallier + +description: | + Resource isolation framework (RIF) is a comprehensive set of hardware blocks + designed to enforce and manage isolation of STM32 hardware resources like + memory and peripherals. + + The RIFSC (RIF security controller) is composed of three sets of registers, + each managing a specific set of hardware resources: + - RISC registers associated with RISUP logic (resource isolation device unit + for peripherals), assign all non-RIF aware peripherals to zero, one or + any security domains (secure, privilege, compartment). + - RIMC registers: associated with RIMU logic (resource isolation master + unit), assign all non RIF-aware bus master to one security domain by + setting secure, privileged and compartment information on the system bus. + Alternatively, the RISUP logic controlling the device port access to a + peripheral can assign target bus attributes to this peripheral master port + (supported attribute: CID). + - RISC registers associated with RISAL logic (resource isolation device unit + for address space - Lite version), assign address space subregions to one + security domains (secure, privilege, compartment). + +properties: + compatible: + contains: + const: st,stm32mp25-rifsc + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + + access-control-provider: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + properties: + access-controller: + minItems: 1 + description: + The phandle of the firewall controller of the peripheral and the + platform-specific firewall ID of the peripheral. + + access-controller-names: + minItems: 1 + + required: + - access-controller + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - access-control-provider + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + access-control-provider; + #access-controller-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + access-controller = <&rifsc 32>; + }; + };