From patchwork Thu Oct 12 09:12:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 13418655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81853CDB46E for ; Thu, 12 Oct 2023 09:12:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235523AbjJLJMd (ORCPT ); Thu, 12 Oct 2023 05:12:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235440AbjJLJMX (ORCPT ); Thu, 12 Oct 2023 05:12:23 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C85A6D7; Thu, 12 Oct 2023 02:12:17 -0700 (PDT) X-UUID: 6c5e26e068df11ee8051498923ad61e6-20231012 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hgkQlNQQVVawmd9UbAc5I3GFHWZ9+VaIhKjxsn2/N7w=; b=V61m/HodW3r4rfVW0CnIjbcfbhFoqOTIM95KjJWEiUwB4CBGfw6jPgCHEBFm1YmApbyYwXf1sw0ocbCsO+q7w8UVwfQ6m7xqrvx9A3bTWJJtmRC8uTuMCQHAMTg42X9C9D+zP+VYY7fIfwTT9H3TGNa2CdXq4P4xJ5gEeccJPsY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:d2232c78-e649-492b-bda1-af17ba5db5fd,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:d948d9bf-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 6c5e26e068df11ee8051498923ad61e6-20231012 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1688458912; Thu, 12 Oct 2023 17:12:10 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 12 Oct 2023 17:12:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 12 Oct 2023 17:12:08 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Ping-Hsun Wu , daoyuan huang , "Hans Verkuil" CC: , , , , Moudy Ho Subject: [PATCH v7 08/12] media: platform: mtk-mdp3: add support for blending multiple components Date: Thu, 12 Oct 2023 17:12:02 +0800 Message-ID: <20231012091206.20165-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231012091206.20165-1-moudy.ho@mediatek.com> References: <20231012091206.20165-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.836800-8.000000 X-TMASE-MatchedRID: zGpV5UNF2R9ILSVPxvZJcHV895e/Bd2JO8xCfog1G6TfUZT83lbkECKI UiL7FC/vhVmF9kz2wxLhgM7lrVqO2A719kpOO37PJQI+kfsRJdq7nrAU9KQxUb/A+0D1to6PuiV mRyWjcdlMmm8bxtFZ3f1/2RbvJIzKGAdnzrnkM48URSScn+QSXt0H8LFZNFG7CKFCmhdu5cWP8S S6hXCztrKbLC5dJ7ThR8h3Q1NFIrZN283DIraxul9QBPvxkHM+LFYB6e8mx8GcZM5WsMfRVz18/ KMzPXz9EZzep1vK6/kXRoPmWO3jekxwdkPqCq7vDEyN+J8hd+jCS9WgDXVPCp6oP1a0mRIj X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.836800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 84424626B5F9B5AED3D7FFE031138AD7CB79695340B3AFE3CE559B102A9C439C2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Certain chips can combine several components to form complex virtual units with advanced functions. These components require simultaneous configuration of their MODs and clocks. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 10 ++++++- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 29 +++++++++++++++++-- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 7 +++++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index a81caf5f472c..f0c5f5abeb23 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -110,17 +110,25 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, /* Set mutex mod */ for (index = 0; index < num_comp; index++) { s32 inner_id = MDP_COMP_NONE; + const u32 *mutex_idx; + const struct mdp_comp_blend *b; if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; + ctx = &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; + + mutex_idx = data->mdp_mutex_table_idx; id = ctx->comp->public_id; - mtk_mutex_write_mod(mutex, data->mdp_mutex_table_idx[id], false); + mtk_mutex_write_mod(mutex, mutex_idx[id], false); + b = &data->comp_data[id].blend; + if (b && b->aid_mod) + mtk_mutex_write_mod(mutex, mutex_idx[b->b_id], false); } mtk_mutex_write_sof(mutex, MUTEX_SOF_IDX_SINGLE_MODE); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 2bf4a6b391b7..b942cc3a1865 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -864,12 +864,26 @@ int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num) int i, ret; for (i = 0; i < num; i++) { + struct mdp_dev *m = comps[i].mdp_dev; + enum mtk_mdp_comp_id id; + const struct mdp_comp_blend *b; + /* Bypass the dummy component*/ - if (!comps[i].mdp_dev) + if (!m) continue; + ret = mdp_comp_clock_on(dev, &comps[i]); if (ret) return ret; + + id = comps[i].public_id; + b = &m->mdp_data->comp_data[id].blend; + + if (b && b->aid_clk) { + ret = mdp_comp_clock_on(dev, m->comp[b->b_id]); + if (ret) + return ret; + } } return 0; @@ -880,10 +894,21 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num) int i; for (i = 0; i < num; i++) { + struct mdp_dev *m = comps[i].mdp_dev; + enum mtk_mdp_comp_id id; + const struct mdp_comp_blend *b; + /* Bypass the dummy component*/ - if (!comps[i].mdp_dev) + if (!m) continue; + mdp_comp_clock_off(dev, &comps[i]); + + id = comps[i].public_id; + b = &m->mdp_data->comp_data[id].blend; + + if (b && b->aid_clk) + mdp_comp_clock_off(dev, m->comp[b->b_id]); } } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index e6cbc6ab6bae..3e5d2da1c807 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -201,9 +201,16 @@ struct mdp_comp_info { u32 dts_reg_ofst; }; +struct mdp_comp_blend { + enum mtk_mdp_comp_id b_id; + bool aid_mod; + bool aid_clk; +}; + struct mdp_comp_data { struct mdp_comp_match match; struct mdp_comp_info info; + struct mdp_comp_blend blend; }; struct mdp_comp_ops;