| Message ID | 20240321-dp-live-fmt-v3-5-d5090d796b7e@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Setting live video input format for ZynqMP DPSUB | expand |
On 21/03/2024 22:43, Anatoliy Klymenko wrote: > Avoid usage of global zynqmp_dpsub.dma_enabled flag in DPSUB layer > context. This flag signals whether the driver runs in DRM CRTC or DRM > bridge mode, assuming that all display layers share the same live or > non-live mode of operation. Using per-layer mode instead of global flag > will simplify future support of the hybrid scenario. > > Remove redundant checks in DMA request/release contexts as > zynqmp_disp_layer.info is well-defined for all layer types, including the > correct number of DMA channels required for each particular layer. > > Signed-off-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> > --- > drivers/gpu/drm/xlnx/zynqmp_disp.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c > index abdc3971b193..0c2b3f4bffa6 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c > @@ -980,7 +980,7 @@ void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) > { > unsigned int i; > > - if (layer->disp->dpsub->dma_enabled) { > + if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) { > for (i = 0; i < layer->drm_fmt->num_planes; i++) > dmaengine_terminate_sync(layer->dmas[i].chan); > } > @@ -1006,7 +1006,7 @@ void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, > > zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); > > - if (!layer->disp->dpsub->dma_enabled) > + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) > return; > > /* > @@ -1044,7 +1044,7 @@ int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, > const struct drm_format_info *info = layer->drm_fmt; > unsigned int i; > > - if (!layer->disp->dpsub->dma_enabled) > + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) > return 0; > > for (i = 0; i < info->num_planes; i++) { > @@ -1094,9 +1094,6 @@ static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, > { > unsigned int i; > > - if (!layer->info || !disp->dpsub->dma_enabled) > - return; > - > for (i = 0; i < layer->info->num_channels; i++) { > struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; > > @@ -1137,9 +1134,6 @@ static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, > unsigned int i; > int ret; > > - if (!disp->dpsub->dma_enabled) > - return 0; > - > for (i = 0; i < layer->info->num_channels; i++) { > struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; > char dma_channel_name[16]; > Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Tomi
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index abdc3971b193..0c2b3f4bffa6 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -980,7 +980,7 @@ void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) { unsigned int i; - if (layer->disp->dpsub->dma_enabled) { + if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) { for (i = 0; i < layer->drm_fmt->num_planes; i++) dmaengine_terminate_sync(layer->dmas[i].chan); } @@ -1006,7 +1006,7 @@ void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); - if (!layer->disp->dpsub->dma_enabled) + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) return; /* @@ -1044,7 +1044,7 @@ int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, const struct drm_format_info *info = layer->drm_fmt; unsigned int i; - if (!layer->disp->dpsub->dma_enabled) + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) return 0; for (i = 0; i < info->num_planes; i++) { @@ -1094,9 +1094,6 @@ static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, { unsigned int i; - if (!layer->info || !disp->dpsub->dma_enabled) - return; - for (i = 0; i < layer->info->num_channels; i++) { struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; @@ -1137,9 +1134,6 @@ static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, unsigned int i; int ret; - if (!disp->dpsub->dma_enabled) - return 0; - for (i = 0; i < layer->info->num_channels; i++) { struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; char dma_channel_name[16];
Avoid usage of global zynqmp_dpsub.dma_enabled flag in DPSUB layer context. This flag signals whether the driver runs in DRM CRTC or DRM bridge mode, assuming that all display layers share the same live or non-live mode of operation. Using per-layer mode instead of global flag will simplify future support of the hybrid scenario. Remove redundant checks in DMA request/release contexts as zynqmp_disp_layer.info is well-defined for all layer types, including the correct number of DMA channels required for each particular layer. Signed-off-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-)