From patchwork Wed Jun 19 14:57:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 13704059 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 111DF7F48C; Wed, 19 Jun 2024 15:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718809287; cv=none; b=NKEtmFpOhYZlXT907Pe3hdwN0FIWX2BbPf2+BVaahCrSq/QjdFv0hJ7h5yxZqLP+LuB81drVbesRKzC5S6PqanVMe/u7kZM0ibl0Vd6s7kDhYfjMOrW5dnld1MTVRmsePDzv4Dhfg0tdU5FTJRdudcWXsMFCEHF/XBa+/C/K/zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718809287; c=relaxed/simple; bh=/JpoivUsM0YtP40dc/NQGjs5b1/rUx1nB9e8nn49HQk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XyqaalGM3FdKLNZY6Qb1cIa3a7AMaSiiLrokDIz7DoGOEBuNgrrxGN1EgIz1RcUsl7Zb+oeAOsz6yKIZs9jISbmxYup0OiK1epX4NSSrK8Fqep4AmrP5rAt4hcIkR14nZMdIv9ll29nNTBmvR1K/NmfZUZUgxbiNi7/F31PezOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=sP4ifP1Y; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="sP4ifP1Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1718809282; bh=/JpoivUsM0YtP40dc/NQGjs5b1/rUx1nB9e8nn49HQk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sP4ifP1YJ0ne4g3JmF0b/ubf5wVMklK223vYla4atz9g7GplCgr3c3SPFzTnk5Ym8 WqbSzfbkS5GlxEPDoMiD+v2ppbsnekl7yd7MmK32jv/aW0Tit2bpMqEZotSSHT+xxD zyYpXlWT4jhd2rYfKE7KnRCoz8ECvYJ6EnGDCMmcrja3m93r5bKfDf2WZShd82VPOp 5Q1XL4m/8oLPoYf65umRALLLhPpiRkU4eeyMb859ZmEO1RryIDKrujDAYuLuO83PB6 xThY7HhK2grF9BYcbNL6cB6hDoYCy1znGnxOIsQVVo6qjdMjWNbR6bA5tze7UvWb5A wTBb95OyyxBbA== Received: from arisu.hitronhub.home (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 947E737821D2; Wed, 19 Jun 2024 15:01:18 +0000 (UTC) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Ezequiel Garcia , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Greg Kroah-Hartman , Sebastian Reichel , Dragan Simic , Diederik de Haas , Andy Yan , Boris Brezillon , Hans Verkuil , Daniel Almeida , Paul Kocialkowski , Nicolas Dufresne , Benjamin Gaignard , Jonas Karlman , Alex Bee , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-staging@lists.linux.dev, Detlev Casanova Subject: [PATCH v2 4/4] arm64: dts: rockchip: Add rkvdec2 Video Decoder on rk3588(s) Date: Wed, 19 Jun 2024 10:57:21 -0400 Message-ID: <20240619150029.59730-5-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240619150029.59730-1-detlev.casanova@collabora.com> References: <20240619150029.59730-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the rkvdec2 Video Decoder to the RK3588s devicetree. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 6ac5ac8b48ab..7690632f57f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2596,6 +2596,16 @@ system_sram2: sram@ff001000 { ranges = <0x0 0x0 0xff001000 0xef000>; #address-cells = <1>; #size-cells = <1>; + + vdec0_sram: rkvdec-sram@0 { + reg = <0x0 0x78000>; + pool; + }; + + vdec1_sram: rkvdec-sram@1 { + reg = <0x78000 0x77000>; + pool; + }; }; pinctrl: pinctrl { @@ -2665,6 +2675,46 @@ gpio4: gpio@fec50000 { #interrupt-cells = <2>; }; }; + + vdec0: video-decoder@fdc38100 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc38100 0x0 0x500>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names = "rst_axi", "rst_ahb", "rst_cabac", + "rst_core", "rst_hevc_cabac"; + power-domains = <&power RK3588_PD_RKVDEC0>; + sram = <&vdec0_sram>; + status = "okay"; + }; + + vdec1: video-decoder@fdc40100 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc40100 0x0 0x500>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names = "rst_axi", "rst_ahb", "rst_cabac", + "rst_core", "rst_hevc_cabac"; + power-domains = <&power RK3588_PD_RKVDEC1>; + sram = <&vdec1_sram>; + status = "okay"; + }; }; #include "rk3588s-pinctrl.dtsi"