| Message ID | 20240627-multistream-v2-2-6ae96c54c1c3@ti.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | media: cadence,ti: CSI2RX Multistream Support | expand |
On 27/06/2024 16:09, Jai Luthra wrote: > The CSI2RX SHIM IP can support a maximum of 32x DMA channels. > > These can be used to split incoming "streams" of data on the CSI-RX > port, distinguished by MIPI Virtual Channel (or Data Type), into > different locations in memory (/dev/videoX nodes). Usually you shouldn't talk about Linux specifics in DT bindings. The DT bindings are only about the HW, and the OS doesn't matter. It doesn't really matter much, but I'd just leave out the mention to /dev/videoX. > Actual number of DMA channels reserved is different for each SoC > integrating this IP, but a maximum of 32x channels are always available > in this IP's register space, so set minimum as 1 and maximum as 32. So in the SoC's dts file you will set the number of channels to the maximum supported by that SoC? I guess that's fine. Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Tomi > Link: https://www.ti.com/lit/pdf/spruiv7 > Signed-off-by: Jai Luthra <j-luthra@ti.com> > --- > .../bindings/media/ti,j721e-csi2rx-shim.yaml | 39 ++++++++++++++++++++-- > 1 file changed, 36 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml > index f762fdc05e4d..0e00533c7b68 100644 > --- a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml > +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml > @@ -20,11 +20,44 @@ properties: > const: ti,j721e-csi2rx-shim > > dmas: > - maxItems: 1 > + minItems: 1 > + maxItems: 32 > > dma-names: > + minItems: 1 > items: > - const: rx0 > + - const: rx1 > + - const: rx2 > + - const: rx3 > + - const: rx4 > + - const: rx5 > + - const: rx6 > + - const: rx7 > + - const: rx8 > + - const: rx9 > + - const: rx10 > + - const: rx11 > + - const: rx12 > + - const: rx13 > + - const: rx14 > + - const: rx15 > + - const: rx16 > + - const: rx17 > + - const: rx18 > + - const: rx19 > + - const: rx20 > + - const: rx21 > + - const: rx22 > + - const: rx23 > + - const: rx24 > + - const: rx25 > + - const: rx26 > + - const: rx27 > + - const: rx28 > + - const: rx29 > + - const: rx30 > + - const: rx31 > > reg: > maxItems: 1 > @@ -62,8 +95,8 @@ examples: > > ti_csi2rx0: ticsi2rx@4500000 { > compatible = "ti,j721e-csi2rx-shim"; > - dmas = <&main_udmap 0x4940>; > - dma-names = "rx0"; > + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>; > + dma-names = "rx0", "rx1"; > reg = <0x4500000 0x1000>; > power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; > #address-cells = <1>; >
diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml index f762fdc05e4d..0e00533c7b68 100644 --- a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml @@ -20,11 +20,44 @@ properties: const: ti,j721e-csi2rx-shim dmas: - maxItems: 1 + minItems: 1 + maxItems: 32 dma-names: + minItems: 1 items: - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: rx4 + - const: rx5 + - const: rx6 + - const: rx7 + - const: rx8 + - const: rx9 + - const: rx10 + - const: rx11 + - const: rx12 + - const: rx13 + - const: rx14 + - const: rx15 + - const: rx16 + - const: rx17 + - const: rx18 + - const: rx19 + - const: rx20 + - const: rx21 + - const: rx22 + - const: rx23 + - const: rx24 + - const: rx25 + - const: rx26 + - const: rx27 + - const: rx28 + - const: rx29 + - const: rx30 + - const: rx31 reg: maxItems: 1 @@ -62,8 +95,8 @@ examples: ti_csi2rx0: ticsi2rx@4500000 { compatible = "ti,j721e-csi2rx-shim"; - dmas = <&main_udmap 0x4940>; - dma-names = "rx0"; + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>; + dma-names = "rx0", "rx1"; reg = <0x4500000 0x1000>; power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>;
The CSI2RX SHIM IP can support a maximum of 32x DMA channels. These can be used to split incoming "streams" of data on the CSI-RX port, distinguished by MIPI Virtual Channel (or Data Type), into different locations in memory (/dev/videoX nodes). Actual number of DMA channels reserved is different for each SoC integrating this IP, but a maximum of 32x channels are always available in this IP's register space, so set minimum as 1 and maximum as 32. Link: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Jai Luthra <j-luthra@ti.com> --- .../bindings/media/ti,j721e-csi2rx-shim.yaml | 39 ++++++++++++++++++++-- 1 file changed, 36 insertions(+), 3 deletions(-)