| Message ID | 20240709160656.31146-8-quic_depengs@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | media: qcom: camss: Add sm8550 support | expand |
On Tue, 09 Jul 2024 21:36:50 +0530, Depeng Shao wrote: > Add bindings for qcom,sm8550-camss in order to support the camera > subsystem for sm8550 > > Co-developed-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> > --- > .../bindings/media/qcom,sm8550-camss.yaml | 545 ++++++++++++++++++ > 1 file changed, 545 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/qcom,sm8550-camss.example.dtb: camss@ace4000: clock-names:34: 'cpas_vfe2' was expected from schema $id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/qcom,sm8550-camss.example.dtb: camss@ace4000: clock-names:38: 'cpas_vfe1' was expected from schema $id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/qcom,sm8550-camss.example.dtb: camss@ace4000: clock-names:41: 'vfe_lite' was expected from schema $id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/qcom,sm8550-camss.example.dtb: camss@ace4000: clock-names:43: 'vfe_lite_csid' was expected from schema $id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240709160656.31146-8-quic_depengs@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 09/07/2024 17:06, Depeng Shao wrote: > Add bindings for qcom,sm8550-camss in order to support the camera > subsystem for sm8550 > > Co-developed-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> > --- Hey Depeng, Thank you for your submission, looks good. I have a few comments below. > + clock-names: > + items: > + - const: cam_ahb_clk > + - const: cam_hf_axi > + - const: cam_sf_axi > + - const: camnoc_axi > + - const: camnoc_axi_src These "_src" clocks are almost certainly not necessary. The CAMCC should have camnoc_axi_src as the parent clock of camnoc_axi, so you don't need ot list the "_src" clock. Please go through this list in your yaml, dts and .c code and remove. There may be an exception where a _src clock is required but my expectation is that all of those _src clocks can be removed. > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. Please name these power-domains in the next iteration of the series. The dependency on the ordering of the power-domains is a bug which new SoC submissions won't be replicating. https://lore.kernel.org/linux-arm-msm/fcdb072d-6099-4423-b4b5-21e9052b82cc@linaro.org/ > + > + interconnects = > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; This tabbing looks weird, do none of the checking tools complain about it ? See: Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml --- bod
On 7/10/2024 5:37 PM, Bryan O'Donoghue wrote: > On 09/07/2024 17:06, Depeng Shao wrote: >> Add bindings for qcom,sm8550-camss in order to support the camera >> subsystem for sm8550 >> >> Co-developed-by: Yongsheng Li <quic_yon@quicinc.com> >> Signed-off-by: Yongsheng Li <quic_yon@quicinc.com> >> Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> >> --- > > Hey Depeng, > > Thank you for your submission, looks good. I have a few comments below. > >> + clock-names: >> + items: >> + - const: cam_ahb_clk >> + - const: cam_hf_axi >> + - const: cam_sf_axi >> + - const: camnoc_axi >> + - const: camnoc_axi_src > > These "_src" clocks are almost certainly not necessary. The CAMCC should > have camnoc_axi_src as the parent clock of camnoc_axi, so you don't need > ot list the "_src" clock. > > Please go through this list in your yaml, dts and .c code and remove. > > There may be an exception where a _src clock is required but my > expectation is that all of those _src clocks can be removed. > > Hey Bryan, Thanks for the reviewing. I will try to move all the _src clk and verify again. >> + power-domains: >> + items: >> + - description: IFE0 GDSC - Image Front End, Global Distributed >> Switch Controller. >> + - description: IFE1 GDSC - Image Front End, Global Distributed >> Switch Controller. >> + - description: IFE2 GDSC - Image Front End, Global Distributed >> Switch Controller. >> + - description: Titan GDSC - Titan ISP Block, Global Distributed >> Switch Controller. > > Please name these power-domains in the next iteration of the series. > > The dependency on the ordering of the power-domains is a bug which new > SoC submissions won't be replicating. > > https://lore.kernel.org/linux-arm-msm/fcdb072d-6099-4423-b4b5-21e9052b82cc@linaro.org/ > Sure, will add this in new patch set. power-domain-names = "ife0", "ife1", "ife2", "top"; >> + >> + interconnects = >> + <&gem_noc MASTER_APPSS_PROC 0 >> &config_noc SLAVE_CAMERA_CFG 0>, >> + <&mmss_noc MASTER_CAMNOC_HF 0 >> &mc_virt SLAVE_EBI1 0>, >> + <&mmss_noc MASTER_CAMNOC_SF 0 >> &mc_virt SLAVE_EBI1 0>, >> + <&mmss_noc MASTER_CAMNOC_ICP 0 >> &mc_virt SLAVE_EBI1 0>; > > This tabbing looks weird, do none of the checking tools complain about it ? > > See: > Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml > Looks like no complain about this, but will update it. > --- > bod Thanks, Depeng
On 09/07/2024 18:06, Depeng Shao wrote: > Add bindings for qcom,sm8550-camss in order to support the camera > subsystem for sm8550 > > Co-developed-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> > --- > .../bindings/media/qcom,sm8550-camss.yaml | 545 ++++++++++++++++++ > 1 file changed, 545 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml > new file mode 100644 > index 000000000000..d002b0ff119e > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml > @@ -0,0 +1,545 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8550 Camera Subsystem (CAMSS) > + > +maintainers: > + - Depeng Shao <quic_depengs@quicinc.com> > + > +description: | Do not need '|' unless you need to preserve formatting. This wasn't tested so I am not going to perform full review. Look at "Re: [PATCH 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding" - all comments apply. ... > + > +required: > + - clock-names > + - clocks > + - compatible Keep the same order as in "properties:'. > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - reg > + - reg-names > + - vdda-phy-supply > + - vdda-pll-supply > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8550-camcc.h> > + #include <dt-bindings/clock/qcom,sm8550-gcc.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + #include <dt-bindings/clock/qcom,rpmh.h> > + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: camss@ace4000 { > + compatible = "qcom,sm8550-camss"; > + > + reg = <0 0x0ace4000 0 0x2000>, > + <0 0x0ace6000 0 0x2000>, > + <0 0x0ace8000 0 0x2000>, > + <0 0x0acea000 0 0x2000>, > + <0 0x0acec000 0 0x2000>, > + <0 0x0acee000 0 0x2000>, > + <0 0x0acf0000 0 0x2000>, > + <0 0x0acf2000 0 0x2000>, > + <0 0x0acb7000 0 0xd00>, > + <0 0x0acb9000 0 0xd00>, > + <0 0x0acbb000 0 0xd00>, > + <0 0x0acca000 0 0xa00>, > + <0 0x0acce000 0 0xa00>, > + <0 0x0acb6000 0 0x1000>, > + <0 0x0ac62000 0 0xf000>, > + <0 0x0ac71000 0 0xf000>, > + <0 0x0ac80000 0 0xf000>, > + <0 0x0acca000 0 0x2800>, > + <0 0x0acce000 0 0x2800>; > + reg-names = "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", These (and many others further) looks misaligned. Best regards, Krzysztof
Hi Krzysztof, On 7/10/2024 7:07 PM, Krzysztof Kozlowski wrote: >> + >> +description: | > > Do not need '|' unless you need to preserve formatting. > > This wasn't tested so I am not going to perform full review. > > Look at "Re: [PATCH 1/6] media: dt-bindings: media: camss: Add > qcom,sc7280-camss binding" - all comments apply. > > ... > Sure, I will follow the comments in https://lore.kernel.org/linux-arm-msm/087e7f29-1fa8-4bc2-bb3d-acb941432381@kernel.org/ >> + >> +required: >> + - clock-names >> + - clocks >> + - compatible > > Keep the same order as in "properties:'. > Sure, I will update it. >> + >> + reg = <0 0x0ace4000 0 0x2000>, >> + <0 0x0ace6000 0 0x2000>, >> + <0 0x0ace8000 0 0x2000>, >> + <0 0x0acea000 0 0x2000>, >> + <0 0x0acec000 0 0x2000>, >> + <0 0x0acee000 0 0x2000>, >> + <0 0x0acf0000 0 0x2000>, >> + <0 0x0acf2000 0 0x2000>, >> + <0 0x0acb7000 0 0xd00>, >> + <0 0x0acb9000 0 0xd00>, >> + <0 0x0acbb000 0 0xd00>, >> + <0 0x0acca000 0 0xa00>, >> + <0 0x0acce000 0 0xa00>, >> + <0 0x0acb6000 0 0x1000>, >> + <0 0x0ac62000 0 0xf000>, >> + <0 0x0ac71000 0 0xf000>, >> + <0 0x0ac80000 0 0xf000>, >> + <0 0x0acca000 0 0x2800>, >> + <0 0x0acce000 0 0x2800>; >> + reg-names = "csiphy0", >> + "csiphy1", >> + "csiphy2", >> + "csiphy3", > > These (and many others further) looks misaligned. > Thanks for pointing out this, will fix this. > Best regards, > Krzysztof > Thanks, Depeng
On 7/9/24 19:06, Depeng Shao wrote: > Add bindings for qcom,sm8550-camss in order to support the camera > subsystem for sm8550 > > Co-developed-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Yongsheng Li <quic_yon@quicinc.com> > Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> > --- > .../bindings/media/qcom,sm8550-camss.yaml | 545 ++++++++++++++++++ > 1 file changed, 545 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml > new file mode 100644 > index 000000000000..d002b0ff119e > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml > @@ -0,0 +1,545 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8550 Camera Subsystem (CAMSS) > + > +maintainers: > + - Depeng Shao <quic_depengs@quicinc.com> > + > +description: | > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,sm8550-camss > + > + clocks: > + minItems: 47 > + maxItems: 47 > + > + clock-names: > + items: > + - const: cam_ahb_clk > + - const: cam_hf_axi > + - const: cam_sf_axi > + - const: camnoc_axi > + - const: camnoc_axi_src > + - const: core_ahb > + - const: cpas_ahb > + - const: slow_ahb_src > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy4 > + - const: csiphy4_timer > + - const: csiphy5 > + - const: csiphy5_timer > + - const: csiphy6 > + - const: csiphy6_timer > + - const: csiphy7 > + - const: csiphy7_timer > + - const: csid_src > + - const: csid > + - const: csiphy_rx > + - const: vfe0_fast_ahb > + - const: vfe0_src > + - const: vfe0 > + - const: cpas_vfe0 > + - const: vfe1_fast_ahb > + - const: vfe1_src > + - const: vfe1 > + - const: cpas_vfe2 > + - const: vfe2_fast_ahb > + - const: vfe2_src > + - const: vfe2 > + - const: cpas_vfe1 > + - const: vfe_lite_ahb > + - const: vfe_lite_csid_src > + - const: vfe_lite > + - const: vfe_lite_cphy_rx > + - const: vfe_lite_csid > + - const: cpas_ife_lite > + - const: cpas_fast_ahb_clk > + - const: fast_ahb_src I believe most of *_src clocks should be removed from the list above as parent clocks with no need for own separate management. > + > + interrupts: > + minItems: 18 > + maxItems: 18 > + > + interrupt-names: > + items: > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: csiphy6 > + - const: csiphy7 > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + iommus: > + maxItems: 1 > + > + interconnects: > + minItems: 4 > + maxItems: 4 > + > + interconnect-names: > + items: > + - const: cam_ahb > + - const: cam_hf_0_mnoc > + - const: cam_sf_0_mnoc > + - const: cam_sf_icp_mnoc > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@2: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@3: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@4: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@5: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + reg: > + minItems: 19 > + maxItems: 19 > + > + reg-names: > + items: > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: csiphy6 > + - const: csiphy7 > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csid_top > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + vdda-phy-supply: > + description: > + Phandle to a regulator supply to PHY core block. > + > + vdda-pll-supply: > + description: > + Phandle to 1.2V regulator supply to PHY refclk pll block. > + > +required: > + - clock-names > + - clocks > + - compatible I would suggest to put 'compatible', 'reg' and 'reg-names' properties as the first ones. 'clock-names' should follow 'clocks' property in the list. > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - reg > + - reg-names > + - vdda-phy-supply > + - vdda-pll-supply > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8550-camcc.h> > + #include <dt-bindings/clock/qcom,sm8550-gcc.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + #include <dt-bindings/clock/qcom,rpmh.h> > + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: camss@ace4000 { > + compatible = "qcom,sm8550-camss"; > + > + reg = <0 0x0ace4000 0 0x2000>, > + <0 0x0ace6000 0 0x2000>, > + <0 0x0ace8000 0 0x2000>, > + <0 0x0acea000 0 0x2000>, > + <0 0x0acec000 0 0x2000>, > + <0 0x0acee000 0 0x2000>, > + <0 0x0acf0000 0 0x2000>, > + <0 0x0acf2000 0 0x2000>, > + <0 0x0acb7000 0 0xd00>, > + <0 0x0acb9000 0 0xd00>, > + <0 0x0acbb000 0 0xd00>, > + <0 0x0acca000 0 0xa00>, > + <0 0x0acce000 0 0xa00>, > + <0 0x0acb6000 0 0x1000>, > + <0 0x0ac62000 0 0xf000>, > + <0 0x0ac71000 0 0xf000>, > + <0 0x0ac80000 0 0xf000>, > + <0 0x0acca000 0 0x2800>, > + <0 0x0acce000 0 0x2800>; > + reg-names = "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "csiphy5", > + "csiphy6", > + "csiphy7", > + "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csid_top", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + vdda-phy-supply = <&vreg_l1e_0p88>; > + vdda-pll-supply = <&vreg_l3e_1p2>; > + > + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; > + > + interrupt-names = "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "csiphy5", > + "csiphy6", > + "csiphy7", > + "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_IFE_2_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, > + <&camcc CAM_CC_CORE_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY3_CLK>, > + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY5_CLK>, > + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY6_CLK>, > + <&camcc CAM_CC_CSI6PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY7_CLK>, > + <&camcc CAM_CC_CSI7PHYTIMER_CLK>, > + <&camcc CAM_CC_CSID_CLK_SRC>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_0_CLK_SRC>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK_SRC>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_2_CLK_SRC>, > + <&camcc CAM_CC_IFE_2_CLK>, > + <&camcc CAM_CC_CPAS_IFE_2_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_FAST_AHB_CLK_SRC>; > + > + clock-names = "cam_ahb_clk", > + "cam_hf_axi", > + "cam_sf_axi", > + "camnoc_axi", > + "camnoc_axi_src", > + "core_ahb", > + "cpas_ahb", > + "slow_ahb_src", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy3", > + "csiphy3_timer", > + "csiphy4", > + "csiphy4_timer", > + "csiphy5", > + "csiphy5_timer", > + "csiphy6", > + "csiphy6_timer", > + "csiphy7", > + "csiphy7_timer", > + "csid_src", > + "csid", > + "csiphy_rx", > + "vfe0_fast_ahb", > + "vfe0_src", > + "vfe0", > + "cpas_vfe0", > + "vfe1_fast_ahb", > + "vfe1_src", > + "vfe1", > + "cpas_vfe1", > + "vfe2_fast_ahb", > + "vfe2_src", > + "vfe2", > + "cpas_vfe2", > + "vfe_lite_ahb", > + "vfe_lite_csid_src", > + "vfe_lite_csid", > + "vfe_lite_cphy_rx", > + "vfe_lite", > + "cpas_ife_lite", > + "cpas_fast_ahb_clk", > + "fast_ahb_src"; > + > + iommus = <&apps_smmu 0x800 0x20>; > + > + interconnects = > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = > + "cam_ahb", > + "cam_hf_0_mnoc", > + "cam_sf_0_mnoc", > + "cam_sf_icp_mnoc"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy_ep0: endpoint@0 { > + reg = <0>; > + clock-lanes = <7>; > + data-lanes = <0 1>; > + remote-endpoint = <&sensor_ep>; > + }; > + }; > + }; > + }; > + }; -- Best wishes, Vladimir
Hi Vladimir, On 8/1/2024 8:05 AM, Vladimir Zapolskiy wrote: > On 7/9/24 19:06, Depeng Shao wrote: >> Add bindings for qcom,sm8550-camss in order to support the camera >> subsystem for sm8550 >> + >> + clock-names: >> + items: >> + - const: cam_ahb_clk >> + - const: cam_hf_axi >> + - const: cam_sf_axi >> + - const: camnoc_axi >> + - const: camnoc_axi_src >> + - const: core_ahb >> + - const: cpas_ahb >> + - const: slow_ahb_src >> + - const: csiphy0 >> + - const: csiphy0_timer >> + - const: csiphy1 >> + - const: csiphy1_timer >> + - const: csiphy2 >> + - const: csiphy2_timer >> + - const: csiphy3 >> + - const: csiphy3_timer >> + - const: csiphy4 >> + - const: csiphy4_timer >> + - const: csiphy5 >> + - const: csiphy5_timer >> + - const: csiphy6 >> + - const: csiphy6_timer >> + - const: csiphy7 >> + - const: csiphy7_timer >> + - const: csid_src >> + - const: csid >> + - const: csiphy_rx >> + - const: vfe0_fast_ahb >> + - const: vfe0_src >> + - const: vfe0 >> + - const: cpas_vfe0 >> + - const: vfe1_fast_ahb >> + - const: vfe1_src >> + - const: vfe1 >> + - const: cpas_vfe2 >> + - const: vfe2_fast_ahb >> + - const: vfe2_src >> + - const: vfe2 >> + - const: cpas_vfe1 >> + - const: vfe_lite_ahb >> + - const: vfe_lite_csid_src >> + - const: vfe_lite >> + - const: vfe_lite_cphy_rx >> + - const: vfe_lite_csid >> + - const: cpas_ife_lite >> + - const: cpas_fast_ahb_clk >> + - const: fast_ahb_src > > I believe most of *_src clocks should be removed from the list above as > parent clocks with no need for own separate management. > Sure, Bryan has same comment, I have removed the *_src clk locally, this change will be in new version patch. >> + >> +required: >> + - clock-names >> + - clocks >> + - compatible > > I would suggest to put 'compatible', 'reg' and 'reg-names' properties as > the first ones. 'clock-names' should follow 'clocks' property in the list. > Thanks for the suggestion, will add it in next version patch. >> + - interconnects >> + - interconnect-names >> + - interrupts >> + - interrupt-names >> + - iommus >> + - power-domains >> + - reg >> + - reg-names >> + - vdda-phy-supply >> + - vdda-pll-supply >> + - ports >> + Thanks, Depeng
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml new file mode 100644 index 000000000000..d002b0ff119e --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml @@ -0,0 +1,545 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Camera Subsystem (CAMSS) + +maintainers: + - Depeng Shao <quic_depengs@quicinc.com> + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8550-camss + + clocks: + minItems: 47 + maxItems: 47 + + clock-names: + items: + - const: cam_ahb_clk + - const: cam_hf_axi + - const: cam_sf_axi + - const: camnoc_axi + - const: camnoc_axi_src + - const: core_ahb + - const: cpas_ahb + - const: slow_ahb_src + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: csiphy6 + - const: csiphy6_timer + - const: csiphy7 + - const: csiphy7_timer + - const: csid_src + - const: csid + - const: csiphy_rx + - const: vfe0_fast_ahb + - const: vfe0_src + - const: vfe0 + - const: cpas_vfe0 + - const: vfe1_fast_ahb + - const: vfe1_src + - const: vfe1 + - const: cpas_vfe2 + - const: vfe2_fast_ahb + - const: vfe2_src + - const: vfe2 + - const: cpas_vfe1 + - const: vfe_lite_ahb + - const: vfe_lite_csid_src + - const: vfe_lite + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: cpas_ife_lite + - const: cpas_fast_ahb_clk + - const: fast_ahb_src + + interrupts: + minItems: 18 + maxItems: 18 + + interrupt-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + iommus: + maxItems: 1 + + interconnects: + minItems: 4 + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_0_mnoc + - const: cam_sf_0_mnoc + - const: cam_sf_icp_mnoc + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + reg: + minItems: 19 + maxItems: 19 + + reg-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_top + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - clock-names + - clocks + - compatible + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - reg + - reg-names + - vdda-phy-supply + - vdda-pll-supply + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-camcc.h> + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@ace4000 { + compatible = "qcom,sm8550-camss"; + + reg = <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0acf0000 0 0x2000>, + <0 0x0acf2000 0 0x2000>, + <0 0x0acb7000 0 0xd00>, + <0 0x0acb9000 0 0xd00>, + <0 0x0acbb000 0 0xd00>, + <0 0x0acca000 0 0xa00>, + <0 0x0acce000 0 0xa00>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0acca000 0 0x2800>, + <0 0x0acce000 0 0x2800>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_top", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY6_CLK>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY7_CLK>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>; + + clock-names = "cam_ahb_clk", + "cam_hf_axi", + "cam_sf_axi", + "camnoc_axi", + "camnoc_axi_src", + "core_ahb", + "cpas_ahb", + "slow_ahb_src", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy6", + "csiphy6_timer", + "csiphy7", + "csiphy7_timer", + "csid_src", + "csid", + "csiphy_rx", + "vfe0_fast_ahb", + "vfe0_src", + "vfe0", + "cpas_vfe0", + "vfe1_fast_ahb", + "vfe1_src", + "vfe1", + "cpas_vfe1", + "vfe2_fast_ahb", + "vfe2_src", + "vfe2", + "cpas_vfe2", + "vfe_lite_ahb", + "vfe_lite_csid_src", + "vfe_lite_csid", + "vfe_lite_cphy_rx", + "vfe_lite", + "cpas_ife_lite", + "cpas_fast_ahb_clk", + "fast_ahb_src"; + + iommus = <&apps_smmu 0x800 0x20>; + + interconnects = + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = + "cam_ahb", + "cam_hf_0_mnoc", + "cam_sf_0_mnoc", + "cam_sf_icp_mnoc"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csiphy_ep0: endpoint@0 { + reg = <0>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + };