From patchwork Tue Dec 10 19:39:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreeya Patel X-Patchwork-Id: 13901971 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA9CD22617A; Tue, 10 Dec 2024 19:41:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733859687; cv=none; b=OJJMa3dJ2Wc0++jxwh8Wntl4sHWc0CU6rl5ctZED07ZlveCdWbn6db0JZFugQq8ujtuGCuQ5r13+RFCbmBeAi08vSr9Kbrw7+CwrMBxFFHRR6nOPNkGRga45bFmFVaqSLFB1DUSrM/JM/NsuCT71fDwEIKH7SFtlaAhY79mjD9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733859687; c=relaxed/simple; bh=QBzH9CuLKr7HcYXPsbeS4iEFc6a5mvd6bQSm9OBbi/E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=clkeWG6KsAH4hSgoDjKOn8pqJCoTLHP0QzD1lFhk/4bzKNV5I+K1l1+4VjmHTOZirVshDvzvaMVuXiuu4clGq0wBD1c97f0MvUbaw2mSplg8hXPzL/n0kLlSD37xj34LaG+hn7mD3zV44ReHnvdRi2uqm6dvnZs9Gq+ssbA7qa4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=CC7DBdBo; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="CC7DBdBo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1733859683; bh=QBzH9CuLKr7HcYXPsbeS4iEFc6a5mvd6bQSm9OBbi/E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CC7DBdBohw45kYyH2NCPwkhATSgGifwgYnDB6dd3dX8bRKYlPA2vbB3hIGwjnztN5 G7Lcm6h64FmF18vtf2fQ2im7hPYz+xDoZ6UmVngXNLQWp/wwMz1CGBhtwV/FMcIaMv UsKtCiJcqqqvx80U+c7HQgSbTOidkbZDsi0f6rNjDb5z5sRzhT66BpSger4OG7EXHi ClQ75edyliXaJjtp/s0swVnUb4oyc4plIYwUTBJweWepy0LwTCEeSB3BJeK2p097NW TE5V+orACvlPzzM9atb9Kc2j2i1ISUwAMScODkusfWZN3NfsSS+MSg750DAn9jNfYL G5lxEe58EvZ8g== Received: from shreeya.shreeya (unknown [110.226.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: shreeya) by bali.collaboradmins.com (Postfix) with ESMTPSA id A4BBB17E37EB; Tue, 10 Dec 2024 20:41:04 +0100 (CET) From: Shreeya Patel To: heiko@sntech.de, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, jose.abreu@synopsys.com, nelson.costa@synopsys.com, shawn.wen@rock-chips.com, nicolas.dufresne@collabora.com, hverkuil@xs4all.nl, hverkuil-cisco@xs4all.nl Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, shreeya.patel@collabora.com, dmitry.osipenko@collabora.com Subject: [RESEND PATCH v5 3/4] arm64: dts: rockchip: Add device tree support for HDMI RX Controller Date: Wed, 11 Dec 2024 01:09:03 +0530 Message-Id: <20241210193904.883225-4-shreeya.patel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241210193904.883225-1-shreeya.patel@collabora.com> References: <20241210193904.883225-1-shreeya.patel@collabora.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add device tree support for Synopsys DesignWare HDMI RX Controller. Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Co-developed-by: Dingxian Wen Signed-off-by: Dingxian Wen Signed-off-by: Shreeya Patel --- Changes in v5 :- - Add alignment property to ensure hdmi-receiver-cma starts at a 64KB-aligned address - Correct one of the interrupt IRQ number Changes in v4 :- - Remove DTS changes added to this patch - Remove the HDMI RX pin nodes as it's already present in the rk3588-base-pinctrl.dtsi Changes in v3 :- - Rename cma node and phandle names - Elaborate the comment to explain 160MiB calculation - Move &hdmi_receiver_cma to the rock5b dts file Changes in v2 :- - Fix some of the checkpatch errors and warnings - Rename resets, vo1-grf and HPD - Move hdmirx_cma node to the rk3588.dtsi file .../dts/rockchip/rk3588-base-pinctrl.dtsi | 14 +++++ .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 57 +++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi index 7f874c77410c..2d4b9986a177 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi @@ -594,6 +594,20 @@ hdmim0_tx1_hpd: hdmim0-tx1-hpd { /* hdmim0_tx1_hpd */ <1 RK_PA6 5 &pcfg_pull_none>; }; + + /omit-if-no-ref/ + hdmim1_rx: hdmim1-rx { + rockchip,pins = + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none_smt>, + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ hdmim1_rx_cec: hdmim1-rx-cec { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index ead151941e84..bde1efdf1824 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -7,6 +7,30 @@ #include "rk3588-extra-pinctrl.dtsi" / { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The 4k HDMI capture controller works only with 32bit + * phys addresses and doesn't support IOMMU. HDMI RX CMA + * must be reserved below 4GB. + * The size of 160MB was determined as follows: + * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB + * To ensure sufficient support for practical use-cases, + * we doubled the 66MB value. + */ + hdmi_receiver_cma: hdmi-receiver-cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x0 0x0 0xffffffff>; + size = <0x0 (160 * 0x100000)>; /* 160MiB */ + alignment = <0x0 0x40000>; /* 64K */ + no-map; + status = "disabled"; + }; + }; + usb_host1_xhci: usb@fc400000 { compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; @@ -135,6 +159,39 @@ i2s10_8ch: i2s@fde00000 { status = "disabled"; }; + hdmi_receiver: hdmi_receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + power-domains = <&power RK3588_PD_VO1>; + rockchip,grf = <&sys_grf>; + rockchip,vo1-grf = <&vo1_grf>; + interrupts = , + , + ; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + memory-region = <&hdmi_receiver_cma>; + pinctrl-0 = <&hdmim1_rx>; + pinctrl-names = "default"; + status = "disabled"; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>;