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HDR mode control is supported, with one HDR mode: staggered HDR with 2 exposures on separate virtual channels. However, for now, only one exposure (VC 0) is accessible via get_frame_desc. Supported resolutions: - 1920 x 1080 @ 60fps (SBGGR10, no HDR) - 1920 x 1080 @ 30fps (SBGGR10, HDR) - 3840 x 2160 @ 30fps (SBGGR12, no HDR) - 3840 x 2160 @ 15fps (SBGGR12, HDR) - 3840 x 2160 @ 30fps (SBGGR10, no HDR) - 3840 x 2160 @ 15fps (SBGGR10, HDR) Signed-off-by: Mirela Rabulea --- Changes in v3: Don't hardcode timing registers: remove timing registers x_output_size/y_output_size from register configuration list, add them to ox05b1s_apply_current_mode Remove HTS,VTS from register config list as they are written by HBLANK and VBLANK controls through __v4l2_ctrl_handler_setup Use const for os08a20_supported_modes os08a20 register config cleaning (remove all registers that were at their default value, and more, keep only what seems mandatory to be able to stream) Let the 4k 10bit mode by default without hdr, all 3 modes are now by default without hdr, staggered hdr may be enabled via v4l2-ctl for any of them. Separate the 10/12 bit register settings into separate lists: os08a20_init_setting_10bit, os08a20_init_setting_12bit Update commit description: rearrange supported resolutions and remove 1 duplicate line, state HDR limitation Increase a bit the default vts for 1080p, to get exactly 60fps, it was 62.61 Use regmap_update_bits() directly and remove ox05b1s_regmap_update_bits() Changes in v2: Add spaces inside brackets, wrap lines to 80 Remove some redundant initialization Use a loop in os08a20_enable_staggered_hdr/os08a20_disable_staggered_hdr, for that, add a register settings array for HDR enabling/disabling Make "sizes" a pointer Remove mode headers, add supported modes in the dedicated c file, ox05b1s_modes.c Refactor register lists, for os08a20 use a common list for all modes, and also specific lists per mode drivers/media/i2c/ox05b1s/ox05b1s.h | 4 + drivers/media/i2c/ox05b1s/ox05b1s_mipi.c | 184 ++++++++++++++++++++++ drivers/media/i2c/ox05b1s/ox05b1s_modes.c | 96 +++++++++++ 3 files changed, 284 insertions(+) diff --git a/drivers/media/i2c/ox05b1s/ox05b1s.h b/drivers/media/i2c/ox05b1s/ox05b1s.h index a893c65894f3..5115060e23cb 100644 --- a/drivers/media/i2c/ox05b1s/ox05b1s.h +++ b/drivers/media/i2c/ox05b1s/ox05b1s.h @@ -17,6 +17,10 @@ struct ox05b1s_reglist { struct ox05b1s_reg *regs; }; +extern struct ox05b1s_reglist os08a20_reglist_4k_10b[]; +extern struct ox05b1s_reglist os08a20_reglist_4k_12b[]; +extern struct ox05b1s_reglist os08a20_reglist_1080p_10b[]; + extern struct ox05b1s_reglist ox05b1s_reglist_2592x1944[]; #endif /* OX05B1S_H */ diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c b/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c index aeea7caa6a15..7dcba5235926 100644 --- a/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c +++ b/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c @@ -40,6 +40,7 @@ struct ox05b1s_sizes { const struct v4l2_area *sizes; }; +struct ox05b1s; struct ox05b1s_plat_data { char name[20]; u32 chip_id; @@ -52,6 +53,9 @@ struct ox05b1s_plat_data { const struct ox05b1s_mode *supported_modes; u32 default_mode_index; const struct ox05b1s_sizes *supported_codes; + const char * const *hdr_modes; + u32 hdr_modes_count; + int (*set_hdr_mode)(struct ox05b1s *sensor, u32 hdr_mode); }; struct ox05b1s_ctrls { @@ -62,6 +66,7 @@ struct ox05b1s_ctrls { struct v4l2_ctrl *vblank; struct v4l2_ctrl *gain; struct v4l2_ctrl *exposure; + struct v4l2_ctrl *hdr_mode; }; struct ox05b1s_mode { @@ -102,6 +107,85 @@ struct ox05b1s { struct ox05b1s_ctrls ctrls; }; +static const struct ox05b1s_mode os08a20_supported_modes[] = { + { + /* 1080p BGGR10, no hdr, 60fps */ + .index = 0, + .width = 1920, + .height = 1080, + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .bpp = 10, + .vts = 0x4d3, + .hts = 0x790, + .exp = 0x4d3 - 8, + .h_bin = true, + .fps = 60, + .reg_data = os08a20_reglist_1080p_10b, + }, { + /* 4k BGGR10, no hdr, 30fps */ + .index = 1, + .width = 3840, + .height = 2160, + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .bpp = 10, + .vts = 0x90a, + .hts = 0x818, + .exp = 0x90a - 8, + .h_bin = false, + .fps = 30, + .reg_data = os08a20_reglist_4k_10b, + }, { + /* 4k BGGR12, no hdr, 30fps */ + .index = 2, + .width = 3840, + .height = 2160, + .code = MEDIA_BUS_FMT_SBGGR12_1X12, + .bpp = 12, + .vts = 0x8f0, + .hts = 0x814, + .exp = 0x8f0 - 8, + .h_bin = false, + .fps = 30, + .reg_data = os08a20_reglist_4k_12b, + }, { + /* sentinel */ + } +}; + +/* keep in sync with os08a20_supported_modes */ +static const struct v4l2_area os08a20_sbggr10_sizes[] = { + { + .width = 1920, + .height = 1080, + }, { + .width = 3840, + .height = 2160, + }, { + /* sentinel */ + } +}; + +static const struct v4l2_area os08a20_sbggr12_sizes[] = { + { + .width = 3840, + .height = 2160, + }, { + /* sentinel */ + } +}; + +static const struct ox05b1s_sizes os08a20_supported_codes[] = { + { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .sizes = os08a20_sbggr10_sizes, + }, { + .code = MEDIA_BUS_FMT_SBGGR12_1X12, + .sizes = os08a20_sbggr12_sizes, + }, { + /* sentinel */ + } +}; + static const struct ox05b1s_mode ox05b1s_supported_modes[] = { { .index = 0, @@ -228,6 +312,62 @@ static int ox05b1s_write_reg_array(struct ox05b1s *sensor, return 0; } +static const char * const os08a20_hdr_modes[] = { + "NO HDR", /* No HDR, single exposure */ + "HDR Staggered", /* Staggered HDR mode, 2 exposures on separate virtual channels */ +}; + +static struct ox05b1s_reg os08a20_init_setting_hdr_en[] = { + { 0x3661, BIT(0) }, /* CORE1[0] STG_HDR_ALIGN_EN */ + { 0x3821, BIT(5) }, /* FORMAT2[5] STG_HDR_EN */ + { 0x4813, BIT(3) }, /* MIPI_CTRL_13[3] */ + { 0x486e, BIT(2) }, /* MIPI_CTRL_6E[2] MIPI_VC_ENABLE */ +}; + +static int os08a20_enable_staggered_hdr(struct ox05b1s *sensor) +{ + int ret; + + for (int i = 0; i < ARRAY_SIZE(os08a20_init_setting_hdr_en); i++) { + ret = regmap_update_bits(sensor->regmap, + os08a20_init_setting_hdr_en[i].addr, + os08a20_init_setting_hdr_en[i].data, + os08a20_init_setting_hdr_en[i].data); + if (ret) + return ret; + } + + return 0; +} + +static int os08a20_disable_staggered_hdr(struct ox05b1s *sensor) +{ + int ret; + + for (int i = 0; i < ARRAY_SIZE(os08a20_init_setting_hdr_en); i++) { + ret = regmap_update_bits(sensor->regmap, + os08a20_init_setting_hdr_en[i].addr, + os08a20_init_setting_hdr_en[i].data, + 0); + if (ret) + return ret; + } + + return 0; +} + +static int os08a20_set_hdr_mode(struct ox05b1s *sensor, u32 hdr_mode) +{ + switch (hdr_mode) { + case 0: + return os08a20_disable_staggered_hdr(sensor); + case 1: + return os08a20_enable_staggered_hdr(sensor); + default: + return -EINVAL; + } +} + static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) { return &container_of(ctrl->handler, struct ox05b1s, @@ -270,6 +410,12 @@ static int ox05b1s_s_ctrl(struct v4l2_ctrl *ctrl) ret = cci_write(sensor->regmap, OX05B1S_REG_EXPOSURE, ctrl->val, NULL); break; + case V4L2_CID_HDR_SENSOR_MODE: + if (sensor->model->set_hdr_mode) + ret = sensor->model->set_hdr_mode(sensor, ctrl->val); + else + ret = -EINVAL; + break; default: ret = -EINVAL; break; @@ -332,6 +478,13 @@ static int ox05b1s_init_controls(struct ox05b1s *sensor) ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN, 0, 0xFFFF, 1, 0x80); + if (sensor->model->hdr_modes) + ctrls->hdr_mode = v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_HDR_SENSOR_MODE, + sensor->model->hdr_modes_count - 1, + 0, 0, sensor->model->hdr_modes); + else + ctrls->hdr_mode = NULL; + if (hdl->error) { ret = hdl->error; goto free_ctrls; @@ -648,7 +801,10 @@ static u8 ox05b1s_code2dt(const u32 code) { switch (code) { case MEDIA_BUS_FMT_SGRBG10_1X10: + case MEDIA_BUS_FMT_SBGGR10_1X10: return MIPI_CSI2_DT_RAW10; + case MEDIA_BUS_FMT_SBGGR12_1X12: + return MIPI_CSI2_DT_RAW12; default: return MIPI_CSI2_DT_RAW10; } @@ -758,6 +914,9 @@ static int ox05b1s_read_chip_id(struct ox05b1s *sensor) } switch (chip_id) { + case 0x530841: + camera_name = "os08a20"; + break; case 0x580542: camera_name = "ox05b1s"; break; @@ -900,6 +1059,24 @@ static void ox05b1s_remove(struct i2c_client *client) static DEFINE_RUNTIME_DEV_PM_OPS(ox05b1s_pm_ops, ox05b1s_runtime_suspend, ox05b1s_runtime_resume, NULL); +static const struct ox05b1s_plat_data os08a20_data = { + .name = "os08a20", + .chip_id = 0x530841, + .native_width = 3872, /* 16 dummy + 3840 active pixels + 16 dummy */ + .native_height = 2192, /* 16 dummy + 2160 active lines + 16 dummy */ + .active_top = 16, + .active_left = 16, + .active_width = 3840, + .active_height = 2160, + .supported_modes = os08a20_supported_modes, + .default_mode_index = 0, + .supported_codes = os08a20_supported_codes, + .hdr_modes = os08a20_hdr_modes, + .hdr_modes_count = ARRAY_SIZE(os08a20_hdr_modes), + .set_hdr_mode = os08a20_set_hdr_mode, + +}; + static const struct ox05b1s_plat_data ox05b1s_data = { .name = "ox05b1s", .chip_id = 0x580542, @@ -912,9 +1089,16 @@ static const struct ox05b1s_plat_data ox05b1s_data = { .supported_modes = ox05b1s_supported_modes, .default_mode_index = 0, .supported_codes = ox05b1s_supported_codes, + .hdr_modes = NULL, + .hdr_modes_count = 0, + .set_hdr_mode = NULL, }; static const struct of_device_id ox05b1s_of_match[] = { + { + .compatible = "ovti,os08a20", + .data = &os08a20_data, + }, { .compatible = "ovti,ox05b1s", .data = &ox05b1s_data, diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_modes.c b/drivers/media/i2c/ox05b1s/ox05b1s_modes.c index 1f3b822d4482..9cfc55f04a70 100644 --- a/drivers/media/i2c/ox05b1s/ox05b1s_modes.c +++ b/drivers/media/i2c/ox05b1s/ox05b1s_modes.c @@ -9,6 +9,102 @@ #include "ox05b1s.h" +/* Common register configuration for Omnivision OS08A20 raw camera */ +struct ox05b1s_reg os08a20_init_setting_common[] = { + { 0x3605, 0x50 }, + { 0x3610, 0x39 }, + { 0x375e, 0x0b }, + { 0x5001, 0x42 }, + { 0x5005, 0x00 }, + { /* sentinel*/ }, +}; + +/* Common register configuration for Omnivision OS08A20 10 bit */ +struct ox05b1s_reg os08a20_init_setting_10bit[] = { + { 0x031e, 0x09 }, + { 0x3609, 0xb5 }, + { 0x3660, 0x43 }, + { 0x3706, 0x35 }, + { 0x370a, 0x00 }, + { 0x370b, 0x98 }, + { 0x3709, 0x49 }, + { /* sentinel*/ }, +}; + +/* Common register configuration for Omnivision OS08A20 12 bit */ +struct ox05b1s_reg os08a20_init_setting_12bit[] = { + { 0x031e, 0x0a }, + { 0x3609, 0xdb }, + { 0x3660, 0xd3 }, + { 0x3706, 0x6a }, + { 0x370a, 0x01 }, + { 0x370b, 0x30 }, + { 0x3709, 0x48 }, + { /* sentinel*/ }, +}; + +/* Mode specific register configurations for Omnivision OS08A20 raw camera */ + +/* OS08A20 3840 x 2160 @30fps BGGR10 no more HDR */ +struct ox05b1s_reg os08a20_init_setting_4k_10b[] = { + { 0x3821, 0x04 }, /* mirror */ + { 0x4837, 0x10 }, /* PCLK PERIOD */ + { /* sentinel*/ }, +}; + +/* OS08A20 3840 x 2160 @30fps BGGR12 */ +struct ox05b1s_reg os08a20_init_setting_4k_12b[] = { + { 0x3821, 0x04 }, /* mirror */ + { 0x4837, 0x10 }, /* PCLK PERIOD */ + { /* sentinel*/ }, +}; + +/* OS08A20 1920 x 1080 @60fps BGGR10 */ +struct ox05b1s_reg os08a20_init_setting_1080p_10b[] = { + { 0x3814, 0x03 }, /* X INC ODD */ + { 0x3816, 0x03 }, /* Y INC ODD */ + { 0x3820, 0x01 }, /* vertical bining */ + { 0x3821, 0x05 }, /* mirror, horizontal bining */ + { 0x4837, 0x16 }, /* PCLK PERIOD */ + { /* sentinel*/ }, +}; + +struct ox05b1s_reglist os08a20_reglist_4k_10b[] = { + { + .regs = os08a20_init_setting_common + }, { + .regs = os08a20_init_setting_10bit + }, { + .regs = os08a20_init_setting_4k_10b + }, { + /* sentinel */ + } +}; + +struct ox05b1s_reglist os08a20_reglist_4k_12b[] = { + { + .regs = os08a20_init_setting_common + }, { + .regs = os08a20_init_setting_12bit + }, { + .regs = os08a20_init_setting_4k_12b + }, { + /* sentinel */ + } +}; + +struct ox05b1s_reglist os08a20_reglist_1080p_10b[] = { + { + .regs = os08a20_init_setting_common + }, { + .regs = os08a20_init_setting_10bit + }, { + .regs = os08a20_init_setting_1080p_10b + }, { + /* sentinel */ + } +}; + /* * Register configuration for Omnivision OX05B1S raw camera * 2592X1944_30FPS_FULL_RGBIr 2592 1944