| Message ID | 20250210162843.609337-5-quic_vikramsa@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | media: qcom: camss: Add sa8775p camss support | expand |
On 10/02/2025 16:28, Vikram Sharma wrote: > Add support for VFE found on SA8775P (Titan 690). This VFE is > different from vfe 780 w.r.t few register offsets. VFE780 with-respect-to a few > It supports two full and five lite VFE. sa8775p supports that not VFE780. > > Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > drivers/media/platform/qcom/camss/Makefile | 1 + > .../media/platform/qcom/camss/camss-vfe-690.c | 163 +++++++++++++++ > drivers/media/platform/qcom/camss/camss-vfe.c | 5 +- > drivers/media/platform/qcom/camss/camss-vfe.h | 1 + > drivers/media/platform/qcom/camss/camss.c | 192 ++++++++++++++++++ > 5 files changed, 361 insertions(+), 1 deletion(-) > create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-690.c > > diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile > index f1d0e9a00220..284f1775f62f 100644 > --- a/drivers/media/platform/qcom/camss/Makefile > +++ b/drivers/media/platform/qcom/camss/Makefile > @@ -18,6 +18,7 @@ qcom-camss-objs += \ > camss-vfe-4-8.o \ > camss-vfe-17x.o \ > camss-vfe-480.o \ > + camss-vfe-690.o \ > camss-vfe-780.o \ > camss-vfe-gen1.o \ > camss-vfe.o \ > diff --git a/drivers/media/platform/qcom/camss/camss-vfe-690.c b/drivers/media/platform/qcom/camss/camss-vfe-690.c > new file mode 100644 > index 000000000000..92c92065f65b > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-vfe-690.c > @@ -0,0 +1,163 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v690 (SA8755P) > + * > + * Copyright (c) 2025 Qualcomm Technologies, Inc. > + */ > + > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > + > +#include "camss.h" > +#include "camss-vfe.h" > + > +#define VFE_TOP_CORE_CFG (0x24) > +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x480 : 0x400) > + > +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) > +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) > + > +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xFC) > + > +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) > +#define WM_CFG_EN BIT(0) > +#define WM_VIR_FRM_EN BIT(1) > +#define WM_CFG_MODE BIT(16) > +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) > +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) > +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) > +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) > +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) > +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) > +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) > + > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) > +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) > +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) > + > +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) > +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) > + > +/* > + * Bus client mapping: > + * > + * VFE: > + * 16 = RDI0, 17 = RDI1, 18 = RDI2 > + * > + * VFE LITE: > + * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5 > + */ > +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n)) > + > +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) > +{ > + struct v4l2_pix_format_mplane *pix = > + &line->video_out.active_fmt.fmt.pix_mp; > + > + wm = RDI_WM(wm); > + > + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); > + /* no clock gating at bus input */ > + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); > + > + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height, > + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); > + writel(WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF, > + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); > + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, > + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); > + > + writel(0x0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); > + > + /* TOP CORE CFG */ > + writel(0x600000, vfe->base + VFE_TOP_CORE_CFG); > + > + /* no dropped frames, one irq per frame */ > + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); > + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); > + > + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); > + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); > + > + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) > +{ > + wm = RDI_WM(wm); > + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, > + struct vfe_line *line) > +{ > + wm = RDI_WM(wm); > + writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); > + > + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", > + wm, addr); > +} > + > +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, false); > +} > + > +static inline void vfe_reg_update_clear(struct vfe_device *vfe, > + enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, true); > +} > + > +static const struct camss_video_ops vfe_video_ops_690 = { > + .queue_buffer = vfe_queue_buffer_v2, > + .flush_buffers = vfe_flush_buffers, > +}; > + > +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) > +{ > + vfe->video_ops = vfe_video_ops_690; > +} > + > +static void vfe_global_reset(struct vfe_device *vfe) > +{ > + vfe_isr_reset_ack(vfe); > +} > + > +static irqreturn_t vfe_isr(int irq, void *dev) > +{ > + /* nop */ > + return IRQ_HANDLED; > +} > + > +static int vfe_halt(struct vfe_device *vfe) > +{ > + /* rely on vfe_disable_output() to stop the VFE */ > + return 0; > +} > + > +const struct vfe_hw_ops vfe_ops_690 = { > + .global_reset = vfe_global_reset, > + .hw_version = vfe_hw_version, > + .isr = vfe_isr, > + .pm_domain_off = vfe_pm_domain_off, > + .pm_domain_on = vfe_pm_domain_on, > + .reg_update = vfe_reg_update, > + .reg_update_clear = vfe_reg_update_clear, > + .subdev_init = vfe_subdev_init, > + .vfe_disable = vfe_disable, > + .vfe_enable = vfe_enable_v2, > + .vfe_halt = vfe_halt, > + .vfe_wm_start = vfe_wm_start, > + .vfe_wm_stop = vfe_wm_stop, > + .vfe_buf_done = vfe_buf_done, > + .vfe_wm_update = vfe_wm_update, > +}; > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c > index 9ffa6bc72cf1..71857c68bbed 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.c > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c > @@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, > case CAMSS_8280XP: > case CAMSS_845: > case CAMSS_8550: > + case CAMSS_8775P: > switch (sink_code) { > case MEDIA_BUS_FMT_YUYV8_1X16: > { > @@ -908,7 +909,8 @@ static int vfe_match_clock_names(struct vfe_device *vfe, > > return (!strcmp(clock->name, vfe_name) || > !strcmp(clock->name, vfe_lite_name) || > - !strcmp(clock->name, "vfe_lite")); > + !strcmp(clock->name, "vfe_lite") || > + !strcmp(clock->name, "camnoc_axi")); Suspicious you really need to add this clock here, shouldn't be necessary unless you are setting the clock to a particular value. > } > > /* > @@ -1972,6 +1974,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) > case CAMSS_8280XP: > case CAMSS_845: > case CAMSS_8550: > + case CAMSS_8775P: > ret = 16; > break; > default: > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h > index 9dec5bc0d1b1..a9322f4440ae 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.h > +++ b/drivers/media/platform/qcom/camss/camss-vfe.h > @@ -243,6 +243,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7; > extern const struct vfe_hw_ops vfe_ops_4_8; > extern const struct vfe_hw_ops vfe_ops_170; > extern const struct vfe_hw_ops vfe_ops_480; > +extern const struct vfe_hw_ops vfe_ops_690; > extern const struct vfe_hw_ops vfe_ops_780; > > int vfe_get(struct vfe_device *vfe); > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index 9458cba1b50f..4df31c89c20c 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -2478,6 +2478,196 @@ static const struct camss_subdev_resources csid_res_8775p[] = { > }, > }; > > +static const struct camss_subdev_resources vfe_res_8775p[] = { > + /* VFE0 */ > + { > + .regulators = {}, > + > + .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb", > + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", > + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", > + "icp_ahb"}, > + .clock_rate = { > + { 0 }, > + { 480000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 0 }, > + { 0 }, > + { 0, 80000000 }, > + { 300000000, 400000000 }, > + { 400000000 }, Is 400 MHz required for camnoc_axi, would 0 i.e. enable not do the same job ? > + { 0 }, > + }, > + > + .reg = { "vfe0" }, > + .interrupt = { "vfe0" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = false, > + .pd_name = NULL, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE1 */ > + { > + .regulators = {}, > + > + .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb", > + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", > + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", > + "icp_ahb"}, > + .clock_rate = { > + { 0 }, > + { 480000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 0 }, > + { 0 }, > + { 0, 80000000 }, > + { 300000000, 400000000 }, > + { 400000000 }, > + { 0 }, > + }, > + > + .reg = { "vfe1" }, > + .interrupt = { "vfe1" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = false, > + .pd_name = NULL, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + redundant newline > + /* VFE2 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite0" }, > + .interrupt = { "vfe-lite0" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE3 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite1" }, > + .interrupt = { "vfe-lite1" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE4 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite2" }, > + .interrupt = { "vfe-lite2" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE5 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite3" }, > + .interrupt = { "vfe-lite3" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE6 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite4" }, > + .interrupt = { "vfe-lite4" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > +}; > + > static const struct resources_icc icc_res_sa8775p[] = { > { > .name = "ahb", > @@ -3469,9 +3659,11 @@ static const struct camss_resources sa8775p_resources = { > .csiphy_res = csiphy_res_8775p, > .csid_res = csid_res_8775p, > .csid_wrapper_res = &csid_wrapper_res_sa8775p, > + .vfe_res = vfe_res_8775p, > .icc_res = icc_res_sa8775p, > .csiphy_num = ARRAY_SIZE(csiphy_res_8775p), > .csid_num = ARRAY_SIZE(csid_res_8775p), > + .vfe_num = ARRAY_SIZE(vfe_res_8775p), > .icc_path_num = ARRAY_SIZE(icc_res_sa8775p), > .link_entities = camss_link_entities > }; I'd rather have the last patch in your series enumerate - fill out - this structure. i.e. vfe and csid 780 should be added and then the enumeration of the resource structure for the sa8775p implementation of 780 as the last patch. --- bod
On 10/02/2025 16:28, Vikram Sharma wrote: > Add support for VFE found on SA8775P (Titan 690). This VFE is > different from vfe 780 w.r.t few register offsets. > It supports two full and five lite VFE. > > Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > drivers/media/platform/qcom/camss/Makefile | 1 + > .../media/platform/qcom/camss/camss-vfe-690.c | 163 +++++++++++++++ > drivers/media/platform/qcom/camss/camss-vfe.c | 5 +- > drivers/media/platform/qcom/camss/camss-vfe.h | 1 + > drivers/media/platform/qcom/camss/camss.c | 192 ++++++++++++++++++ > 5 files changed, 361 insertions(+), 1 deletion(-) > create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-690.c > > diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile > index f1d0e9a00220..284f1775f62f 100644 > --- a/drivers/media/platform/qcom/camss/Makefile > +++ b/drivers/media/platform/qcom/camss/Makefile > @@ -18,6 +18,7 @@ qcom-camss-objs += \ > camss-vfe-4-8.o \ > camss-vfe-17x.o \ > camss-vfe-480.o \ > + camss-vfe-690.o \ > camss-vfe-780.o \ > camss-vfe-gen1.o \ > camss-vfe.o \ > diff --git a/drivers/media/platform/qcom/camss/camss-vfe-690.c b/drivers/media/platform/qcom/camss/camss-vfe-690.c > new file mode 100644 > index 000000000000..92c92065f65b > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-vfe-690.c > @@ -0,0 +1,163 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v690 (SA8755P) > + * > + * Copyright (c) 2025 Qualcomm Technologies, Inc. > + */ > + > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > + > +#include "camss.h" > +#include "camss-vfe.h" > + > +#define VFE_TOP_CORE_CFG (0x24) > +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x480 : 0x400) > + > +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) > +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) > + > +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xFC) > + > +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) > +#define WM_CFG_EN BIT(0) > +#define WM_VIR_FRM_EN BIT(1) > +#define WM_CFG_MODE BIT(16) > +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) > +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) > +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) > +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) > +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) > +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) > +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) > + > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) > +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) > +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) > + > +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) > +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) > + > +/* > + * Bus client mapping: > + * > + * VFE: > + * 16 = RDI0, 17 = RDI1, 18 = RDI2 > + * > + * VFE LITE: > + * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5 > + */ > +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n)) > + > +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) > +{ > + struct v4l2_pix_format_mplane *pix = > + &line->video_out.active_fmt.fmt.pix_mp; > + > + wm = RDI_WM(wm); > + > + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); > + /* no clock gating at bus input */ > + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); > + > + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height, > + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); > + writel(WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF, > + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); > + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, > + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); > + > + writel(0x0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); > + > + /* TOP CORE CFG */ > + writel(0x600000, vfe->base + VFE_TOP_CORE_CFG); > + > + /* no dropped frames, one irq per frame */ > + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); > + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); > + > + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); > + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); > + > + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) > +{ > + wm = RDI_WM(wm); > + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, > + struct vfe_line *line) > +{ > + wm = RDI_WM(wm); > + writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); > + > + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", > + wm, addr); > +} > + > +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, false); > +} > + > +static inline void vfe_reg_update_clear(struct vfe_device *vfe, > + enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, true); > +} > + > +static const struct camss_video_ops vfe_video_ops_690 = { > + .queue_buffer = vfe_queue_buffer_v2, > + .flush_buffers = vfe_flush_buffers, > +}; > + > +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) > +{ > + vfe->video_ops = vfe_video_ops_690; > +} > + > +static void vfe_global_reset(struct vfe_device *vfe) > +{ > + vfe_isr_reset_ack(vfe); > +} > + > +static irqreturn_t vfe_isr(int irq, void *dev) > +{ > + /* nop */ > + return IRQ_HANDLED; > +} > + > +static int vfe_halt(struct vfe_device *vfe) > +{ > + /* rely on vfe_disable_output() to stop the VFE */ > + return 0; > +} > + > +const struct vfe_hw_ops vfe_ops_690 = { > + .global_reset = vfe_global_reset, > + .hw_version = vfe_hw_version, > + .isr = vfe_isr, > + .pm_domain_off = vfe_pm_domain_off, > + .pm_domain_on = vfe_pm_domain_on, > + .reg_update = vfe_reg_update, > + .reg_update_clear = vfe_reg_update_clear, > + .subdev_init = vfe_subdev_init, > + .vfe_disable = vfe_disable, > + .vfe_enable = vfe_enable_v2, > + .vfe_halt = vfe_halt, > + .vfe_wm_start = vfe_wm_start, > + .vfe_wm_stop = vfe_wm_stop, > + .vfe_buf_done = vfe_buf_done, > + .vfe_wm_update = vfe_wm_update, > +}; > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c > index 9ffa6bc72cf1..71857c68bbed 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.c > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c > @@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, > case CAMSS_8280XP: > case CAMSS_845: > case CAMSS_8550: > + case CAMSS_8775P: > switch (sink_code) { > case MEDIA_BUS_FMT_YUYV8_1X16: > { > @@ -908,7 +909,8 @@ static int vfe_match_clock_names(struct vfe_device *vfe, > > return (!strcmp(clock->name, vfe_name) || > !strcmp(clock->name, vfe_lite_name) || > - !strcmp(clock->name, "vfe_lite")); > + !strcmp(clock->name, "vfe_lite") || > + !strcmp(clock->name, "camnoc_axi")); > } > > /* > @@ -1972,6 +1974,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) > case CAMSS_8280XP: > case CAMSS_845: > case CAMSS_8550: > + case CAMSS_8775P: > ret = 16; > break; > default: > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h > index 9dec5bc0d1b1..a9322f4440ae 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.h > +++ b/drivers/media/platform/qcom/camss/camss-vfe.h > @@ -243,6 +243,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7; > extern const struct vfe_hw_ops vfe_ops_4_8; > extern const struct vfe_hw_ops vfe_ops_170; > extern const struct vfe_hw_ops vfe_ops_480; > +extern const struct vfe_hw_ops vfe_ops_690; > extern const struct vfe_hw_ops vfe_ops_780; > > int vfe_get(struct vfe_device *vfe); > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index 9458cba1b50f..4df31c89c20c 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -2478,6 +2478,196 @@ static const struct camss_subdev_resources csid_res_8775p[] = { > }, > }; > > +static const struct camss_subdev_resources vfe_res_8775p[] = { > + /* VFE0 */ > + { > + .regulators = {}, > + > + .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb", > + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", > + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", > + "icp_ahb"}, > + .clock_rate = { > + { 0 }, > + { 480000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 0 }, > + { 0 }, > + { 0, 80000000 }, > + { 300000000, 400000000 }, > + { 400000000 }, > + { 0 }, > + }, > + > + .reg = { "vfe0" }, > + .interrupt = { "vfe0" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = false, > + .pd_name = NULL, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE1 */ > + { > + .regulators = {}, > + > + .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb", > + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", > + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", > + "icp_ahb"}, > + .clock_rate = { > + { 0 }, > + { 480000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 0 }, > + { 0 }, > + { 0, 80000000 }, > + { 300000000, 400000000 }, > + { 400000000 }, > + { 0 }, > + }, > + > + .reg = { "vfe1" }, > + .interrupt = { "vfe1" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = false, > + .pd_name = NULL, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + > + /* VFE2 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite0" }, > + .interrupt = { "vfe-lite0" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE3 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite1" }, > + .interrupt = { "vfe-lite1" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE4 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite2" }, > + .interrupt = { "vfe-lite2" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE5 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite3" }, > + .interrupt = { "vfe-lite3" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE6 (lite) */ > + { > + .regulators = {}, > + > + .clock = { "cpas_ife_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 0, 0 }, > + { 300000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 400000000, 400000000, 400000000, 400000000 }, > + { 480000000, 600000000, 600000000, 600000000 }, > + }, > + .reg = { "vfe_lite4" }, > + .interrupt = { "vfe-lite4" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_690, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > +}; > + > static const struct resources_icc icc_res_sa8775p[] = { > { > .name = "ahb", > @@ -3469,9 +3659,11 @@ static const struct camss_resources sa8775p_resources = { > .csiphy_res = csiphy_res_8775p, > .csid_res = csid_res_8775p, > .csid_wrapper_res = &csid_wrapper_res_sa8775p, > + .vfe_res = vfe_res_8775p, > .icc_res = icc_res_sa8775p, > .csiphy_num = ARRAY_SIZE(csiphy_res_8775p), > .csid_num = ARRAY_SIZE(csid_res_8775p), > + .vfe_num = ARRAY_SIZE(vfe_res_8775p), > .icc_path_num = ARRAY_SIZE(icc_res_sa8775p), > .link_entities = camss_link_entities > }; There's a pretty superficial difference between 780 and 990 git diff drivers/media/platform/qcom/camss/camss-vfe-690.c drivers/media/platform/qcom/camss/camss-vfe-780.c linux-media-qcom-camss/master? 3c3 < * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v690 (SA8755P) --- > * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550) 5c5 < * Copyright (c) 2025 Qualcomm Technologies, Inc. --- > * Copyright (c) 2024 Qualcomm Technologies, Inc. 15,16c15 < #define VFE_TOP_CORE_CFG (0x24) < #define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x480 : 0x400) --- > #define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00) 19c18 < #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) --- > #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) 21c20 < #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xFC) --- > #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC) 46,47c45,46 < * VFE: < * 16 = RDI0, 17 = RDI1, 18 = RDI2 --- > * Full VFE: > * 23 = RDI0, 24 = RDI1, 25 = RDI2 50c49 < * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5 --- > * 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4 52c51 < #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n)) --- > #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) 61d59 < writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); 62a61,62 > writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); > 65c65 < writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height, --- > writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, 67c67 < writel(WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF, --- > writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), 71,75c71 < < writel(0x0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); < < /* TOP CORE CFG */ < writel(0x600000, vfe->base + VFE_TOP_CORE_CFG); What's this for ? --- > writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); 99c95 < writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); --- > writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); 120c116 < static const struct camss_video_ops vfe_video_ops_690 = { --- > static const struct camss_video_ops vfe_video_ops_780 = { 127c123 < vfe->video_ops = vfe_video_ops_690; --- > vfe->video_ops = vfe_video_ops_780; 147c143 < const struct vfe_hw_ops vfe_ops_690 = { --- > const struct vfe_hw_ops vfe_ops_780 = { I don't really see much logical difference here to justify all of the copy/paste code. Could you comment on some set of offsets passed in the VFE resources structure ? If not an offset then perhaps a camss-vfe-gen3.c file which contains the shared code and wrappering that shared code in camss-vfe-690 and vfe-780 respectively ? Actually, I think that's the way to go, for his level of similarity it should be possible to move the share code 1:1 in many cases to a shared file. --- bod
On 2/11/2025 1:44 AM, Bryan O'Donoghue wrote: > On 10/02/2025 16:28, Vikram Sharma wrote: >> Add support for VFE found on SA8775P (Titan 690). This VFE is >> different from vfe 780 w.r.t few register offsets. > > VFE780 > > with-respect-to a few > >> It supports two full and five lite VFE. > > sa8775p supports that not VFE780. Hi Bryan, Thanks for your comments. Will rephrase commit text. > >> >> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> >> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> >> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >> --- >> drivers/media/platform/qcom/camss/Makefile | 1 + >> .../media/platform/qcom/camss/camss-vfe-690.c | 163 +++++++++++++++ >> drivers/media/platform/qcom/camss/camss-vfe.c | 5 +- >> drivers/media/platform/qcom/camss/camss-vfe.h | 1 + >> drivers/media/platform/qcom/camss/camss.c | 192 ++++++++++++++++++ >> 5 files changed, 361 insertions(+), 1 deletion(-) >> create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-690.c >> >> diff --git a/drivers/media/platform/qcom/camss/Makefile >> b/drivers/media/platform/qcom/camss/Makefile >> index f1d0e9a00220..284f1775f62f 100644 >> --- a/drivers/media/platform/qcom/camss/Makefile >> +++ b/drivers/media/platform/qcom/camss/Makefile >> @@ -18,6 +18,7 @@ qcom-camss-objs += \ >> camss-vfe-4-8.o \ >> camss-vfe-17x.o \ >> camss-vfe-480.o \ >> + camss-vfe-690.o \ >> camss-vfe-780.o \ >> camss-vfe-gen1.o \ >> camss-vfe.o \ >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-690.c >> b/drivers/media/platform/qcom/camss/camss-vfe-690.c >> new file mode 100644 >> index 000000000000..92c92065f65b >> --- /dev/null >> +++ b/drivers/media/platform/qcom/camss/camss-vfe-690.c >> @@ -0,0 +1,163 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v690 >> (SA8755P) >> + * >> + * Copyright (c) 2025 Qualcomm Technologies, Inc. >> + */ >> + >> +#include <linux/interrupt.h> >> +#include <linux/io.h> >> +#include <linux/iopoll.h> >> + >> +#include "camss.h" >> +#include "camss-vfe.h" >> + >> +#define VFE_TOP_CORE_CFG (0x24) >> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x480 : 0x400) >> + >> +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) >> +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) >> + >> +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xFC) >> + >> +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) >> +#define WM_CFG_EN BIT(0) >> +#define WM_VIR_FRM_EN BIT(1) >> +#define WM_CFG_MODE BIT(16) >> +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * >> 0x100) >> +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * >> 0x100) >> +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * >> 0x100) >> +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) >> +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * >> 0x100) >> +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) >> +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * >> 0x100) >> + >> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 >> + (n) * 0x100) >> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 >> + (n) * 0x100) >> +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 >> + (n) * 0x100) >> +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c >> + (n) * 0x100) >> + >> +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 >> + (n) * 0x100) >> +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + >> 0x264 + (n) * 0x100) >> + >> +/* >> + * Bus client mapping: >> + * >> + * VFE: >> + * 16 = RDI0, 17 = RDI1, 18 = RDI2 >> + * >> + * VFE LITE: >> + * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5 >> + */ >> +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n)) >> + >> +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct >> vfe_line *line) >> +{ >> + struct v4l2_pix_format_mplane *pix = >> + &line->video_out.active_fmt.fmt.pix_mp; >> + >> + wm = RDI_WM(wm); >> + >> + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); >> + /* no clock gating at bus input */ >> + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); >> + >> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height, >> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); >> + writel(WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF, >> + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); >> + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, >> + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); >> + >> + writel(0x0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); >> + >> + /* TOP CORE CFG */ >> + writel(0x600000, vfe->base + VFE_TOP_CORE_CFG); >> + >> + /* no dropped frames, one irq per frame */ >> + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); >> + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); >> + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); >> + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); >> + >> + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); >> + writel(0xFFFFFFFF, vfe->base + >> VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); >> + >> + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); >> +} >> + >> +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) >> +{ >> + wm = RDI_WM(wm); >> + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); >> +} >> + >> +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, >> + struct vfe_line *line) >> +{ >> + wm = RDI_WM(wm); >> + writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); >> + >> + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", >> + wm, addr); >> +} >> + >> +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id >> line_id) >> +{ >> + int port_id = line_id; >> + >> + camss_reg_update(vfe->camss, vfe->id, port_id, false); >> +} >> + >> +static inline void vfe_reg_update_clear(struct vfe_device *vfe, >> + enum vfe_line_id line_id) >> +{ >> + int port_id = line_id; >> + >> + camss_reg_update(vfe->camss, vfe->id, port_id, true); >> +} >> + >> +static const struct camss_video_ops vfe_video_ops_690 = { >> + .queue_buffer = vfe_queue_buffer_v2, >> + .flush_buffers = vfe_flush_buffers, >> +}; >> + >> +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) >> +{ >> + vfe->video_ops = vfe_video_ops_690; >> +} >> + >> +static void vfe_global_reset(struct vfe_device *vfe) >> +{ >> + vfe_isr_reset_ack(vfe); >> +} >> + >> +static irqreturn_t vfe_isr(int irq, void *dev) >> +{ >> + /* nop */ >> + return IRQ_HANDLED; >> +} >> + >> +static int vfe_halt(struct vfe_device *vfe) >> +{ >> + /* rely on vfe_disable_output() to stop the VFE */ >> + return 0; >> +} >> + >> +const struct vfe_hw_ops vfe_ops_690 = { >> + .global_reset = vfe_global_reset, >> + .hw_version = vfe_hw_version, >> + .isr = vfe_isr, >> + .pm_domain_off = vfe_pm_domain_off, >> + .pm_domain_on = vfe_pm_domain_on, >> + .reg_update = vfe_reg_update, >> + .reg_update_clear = vfe_reg_update_clear, >> + .subdev_init = vfe_subdev_init, >> + .vfe_disable = vfe_disable, >> + .vfe_enable = vfe_enable_v2, >> + .vfe_halt = vfe_halt, >> + .vfe_wm_start = vfe_wm_start, >> + .vfe_wm_stop = vfe_wm_stop, >> + .vfe_buf_done = vfe_buf_done, >> + .vfe_wm_update = vfe_wm_update, >> +}; >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c >> b/drivers/media/platform/qcom/camss/camss-vfe.c >> index 9ffa6bc72cf1..71857c68bbed 100644 >> --- a/drivers/media/platform/qcom/camss/camss-vfe.c >> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c >> @@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line >> *line, u32 sink_code, >> case CAMSS_8280XP: >> case CAMSS_845: >> case CAMSS_8550: >> + case CAMSS_8775P: >> switch (sink_code) { >> case MEDIA_BUS_FMT_YUYV8_1X16: >> { >> @@ -908,7 +909,8 @@ static int vfe_match_clock_names(struct >> vfe_device *vfe, >> return (!strcmp(clock->name, vfe_name) || >> !strcmp(clock->name, vfe_lite_name) || >> - !strcmp(clock->name, "vfe_lite")); >> + !strcmp(clock->name, "vfe_lite") || >> + !strcmp(clock->name, "camnoc_axi")); > > Suspicious you really need to add this clock here, shouldn't be > necessary unless you are setting the clock to a particular value. While testing we found that if camnoc_axi not set to a particular level i.e. 400Mhz Overflows were seen on csid output. > >> } >> /* >> @@ -1972,6 +1974,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) >> case CAMSS_8280XP: >> case CAMSS_845: >> case CAMSS_8550: >> + case CAMSS_8775P: >> ret = 16; >> break; >> default: >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h >> b/drivers/media/platform/qcom/camss/camss-vfe.h >> index 9dec5bc0d1b1..a9322f4440ae 100644 >> --- a/drivers/media/platform/qcom/camss/camss-vfe.h >> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h >> @@ -243,6 +243,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7; >> extern const struct vfe_hw_ops vfe_ops_4_8; >> extern const struct vfe_hw_ops vfe_ops_170; >> extern const struct vfe_hw_ops vfe_ops_480; >> +extern const struct vfe_hw_ops vfe_ops_690; >> extern const struct vfe_hw_ops vfe_ops_780; >> int vfe_get(struct vfe_device *vfe); >> diff --git a/drivers/media/platform/qcom/camss/camss.c >> b/drivers/media/platform/qcom/camss/camss.c >> index 9458cba1b50f..4df31c89c20c 100644 >> --- a/drivers/media/platform/qcom/camss/camss.c >> +++ b/drivers/media/platform/qcom/camss/camss.c >> @@ -2478,6 +2478,196 @@ static const struct camss_subdev_resources >> csid_res_8775p[] = { >> }, >> }; >> +static const struct camss_subdev_resources vfe_res_8775p[] = { >> + /* VFE0 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb", >> + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", >> + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", >> + "icp_ahb"}, >> + .clock_rate = { >> + { 0 }, >> + { 480000000 }, >> + { 300000000, 400000000 }, >> + { 300000000, 400000000 }, >> + { 0 }, >> + { 0 }, >> + { 0, 80000000 }, >> + { 300000000, 400000000 }, >> + { 400000000 }, > > Is 400 MHz required for camnoc_axi, would 0 i.e. enable not do the > same job? While testing we found that if camnoc_axi not set to a particular level i.e. 400Mhz Overflows were seen on csid output. > >> + { 0 }, >> + }, >> + >> + .reg = { "vfe0" }, >> + .interrupt = { "vfe0" }, >> + .vfe = { >> + .line_num = 3, >> + .is_lite = false, >> + .has_pd = false, >> + .pd_name = NULL, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE1 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb", >> + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", >> + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", >> + "icp_ahb"}, >> + .clock_rate = { >> + { 0 }, >> + { 480000000 }, >> + { 300000000, 400000000 }, >> + { 300000000, 400000000 }, >> + { 0 }, >> + { 0 }, >> + { 0, 80000000 }, >> + { 300000000, 400000000 }, >> + { 400000000 }, >> + { 0 }, >> + }, >> + >> + .reg = { "vfe1" }, >> + .interrupt = { "vfe1" }, >> + .vfe = { >> + .line_num = 3, >> + .is_lite = false, >> + .has_pd = false, >> + .pd_name = NULL, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + > > redundant newline ACK > >> + /* VFE2 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite0" }, >> + .interrupt = { "vfe-lite0" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE3 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite1" }, >> + .interrupt = { "vfe-lite1" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE4 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite2" }, >> + .interrupt = { "vfe-lite2" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE5 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite3" }, >> + .interrupt = { "vfe-lite3" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE6 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite4" }, >> + .interrupt = { "vfe-lite4" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> +}; >> + >> static const struct resources_icc icc_res_sa8775p[] = { >> { >> .name = "ahb", >> @@ -3469,9 +3659,11 @@ static const struct camss_resources >> sa8775p_resources = { >> .csiphy_res = csiphy_res_8775p, >> .csid_res = csid_res_8775p, >> .csid_wrapper_res = &csid_wrapper_res_sa8775p, >> + .vfe_res = vfe_res_8775p, >> .icc_res = icc_res_sa8775p, >> .csiphy_num = ARRAY_SIZE(csiphy_res_8775p), >> .csid_num = ARRAY_SIZE(csid_res_8775p), >> + .vfe_num = ARRAY_SIZE(vfe_res_8775p), >> .icc_path_num = ARRAY_SIZE(icc_res_sa8775p), >> .link_entities = camss_link_entities >> }; > > I'd rather have the last patch in your series enumerate - fill out - > this structure. > > i.e. vfe and csid 780 should be added and then the enumeration of the > resource structure for the sa8775p implementation of 780 as the last > patch. Does that mean we should add compatible string, new enum "CAMSS_8775P" and enumerations of the resources as the last patch of the series? Best Regards, Vikram > > --- > bod
On 2/11/2025 2:08 AM, Bryan O'Donoghue wrote: > On 10/02/2025 16:28, Vikram Sharma wrote: >> Add support for VFE found on SA8775P (Titan 690). This VFE is >> different from vfe 780 w.r.t few register offsets. >> It supports two full and five lite VFE. >> >> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> >> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> >> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >> --- >> drivers/media/platform/qcom/camss/Makefile | 1 + >> .../media/platform/qcom/camss/camss-vfe-690.c | 163 +++++++++++++++ >> drivers/media/platform/qcom/camss/camss-vfe.c | 5 +- >> drivers/media/platform/qcom/camss/camss-vfe.h | 1 + >> drivers/media/platform/qcom/camss/camss.c | 192 ++++++++++++++++++ >> 5 files changed, 361 insertions(+), 1 deletion(-) >> create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-690.c >> >> diff --git a/drivers/media/platform/qcom/camss/Makefile >> b/drivers/media/platform/qcom/camss/Makefile >> index f1d0e9a00220..284f1775f62f 100644 >> --- a/drivers/media/platform/qcom/camss/Makefile >> +++ b/drivers/media/platform/qcom/camss/Makefile >> @@ -18,6 +18,7 @@ qcom-camss-objs += \ >> camss-vfe-4-8.o \ >> camss-vfe-17x.o \ >> camss-vfe-480.o \ >> + camss-vfe-690.o \ >> camss-vfe-780.o \ >> camss-vfe-gen1.o \ >> camss-vfe.o \ >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-690.c >> b/drivers/media/platform/qcom/camss/camss-vfe-690.c >> new file mode 100644 >> index 000000000000..92c92065f65b >> --- /dev/null >> +++ b/drivers/media/platform/qcom/camss/camss-vfe-690.c >> @@ -0,0 +1,163 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v690 >> (SA8755P) >> + * >> + * Copyright (c) 2025 Qualcomm Technologies, Inc. >> + */ >> + >> +#include <linux/interrupt.h> >> +#include <linux/io.h> >> +#include <linux/iopoll.h> >> + >> +#include "camss.h" >> +#include "camss-vfe.h" >> + >> +#define VFE_TOP_CORE_CFG (0x24) >> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x480 : 0x400) >> + >> +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) >> +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) >> + >> +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xFC) >> + >> +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) >> +#define WM_CFG_EN BIT(0) >> +#define WM_VIR_FRM_EN BIT(1) >> +#define WM_CFG_MODE BIT(16) >> +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * >> 0x100) >> +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * >> 0x100) >> +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * >> 0x100) >> +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) >> +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * >> 0x100) >> +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) >> +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * >> 0x100) >> + >> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 >> + (n) * 0x100) >> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 >> + (n) * 0x100) >> +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 >> + (n) * 0x100) >> +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c >> + (n) * 0x100) >> + >> +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 >> + (n) * 0x100) >> +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + >> 0x264 + (n) * 0x100) >> + >> +/* >> + * Bus client mapping: >> + * >> + * VFE: >> + * 16 = RDI0, 17 = RDI1, 18 = RDI2 >> + * >> + * VFE LITE: >> + * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5 >> + */ >> +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n)) >> + >> +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct >> vfe_line *line) >> +{ >> + struct v4l2_pix_format_mplane *pix = >> + &line->video_out.active_fmt.fmt.pix_mp; >> + >> + wm = RDI_WM(wm); >> + >> + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); >> + /* no clock gating at bus input */ >> + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); >> + >> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height, >> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); >> + writel(WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF, >> + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); >> + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, >> + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); >> + >> + writel(0x0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); >> + >> + /* TOP CORE CFG */ >> + writel(0x600000, vfe->base + VFE_TOP_CORE_CFG); >> + >> + /* no dropped frames, one irq per frame */ >> + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); >> + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); >> + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); >> + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); >> + >> + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); >> + writel(0xFFFFFFFF, vfe->base + >> VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); >> + >> + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); >> +} >> + >> +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) >> +{ >> + wm = RDI_WM(wm); >> + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); >> +} >> + >> +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, >> + struct vfe_line *line) >> +{ >> + wm = RDI_WM(wm); >> + writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); >> + >> + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", >> + wm, addr); >> +} >> + >> +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id >> line_id) >> +{ >> + int port_id = line_id; >> + >> + camss_reg_update(vfe->camss, vfe->id, port_id, false); >> +} >> + >> +static inline void vfe_reg_update_clear(struct vfe_device *vfe, >> + enum vfe_line_id line_id) >> +{ >> + int port_id = line_id; >> + >> + camss_reg_update(vfe->camss, vfe->id, port_id, true); >> +} >> + >> +static const struct camss_video_ops vfe_video_ops_690 = { >> + .queue_buffer = vfe_queue_buffer_v2, >> + .flush_buffers = vfe_flush_buffers, >> +}; >> + >> +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) >> +{ >> + vfe->video_ops = vfe_video_ops_690; >> +} >> + >> +static void vfe_global_reset(struct vfe_device *vfe) >> +{ >> + vfe_isr_reset_ack(vfe); >> +} >> + >> +static irqreturn_t vfe_isr(int irq, void *dev) >> +{ >> + /* nop */ >> + return IRQ_HANDLED; >> +} >> + >> +static int vfe_halt(struct vfe_device *vfe) >> +{ >> + /* rely on vfe_disable_output() to stop the VFE */ >> + return 0; >> +} >> + >> +const struct vfe_hw_ops vfe_ops_690 = { >> + .global_reset = vfe_global_reset, >> + .hw_version = vfe_hw_version, >> + .isr = vfe_isr, >> + .pm_domain_off = vfe_pm_domain_off, >> + .pm_domain_on = vfe_pm_domain_on, >> + .reg_update = vfe_reg_update, >> + .reg_update_clear = vfe_reg_update_clear, >> + .subdev_init = vfe_subdev_init, >> + .vfe_disable = vfe_disable, >> + .vfe_enable = vfe_enable_v2, >> + .vfe_halt = vfe_halt, >> + .vfe_wm_start = vfe_wm_start, >> + .vfe_wm_stop = vfe_wm_stop, >> + .vfe_buf_done = vfe_buf_done, >> + .vfe_wm_update = vfe_wm_update, >> +}; >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c >> b/drivers/media/platform/qcom/camss/camss-vfe.c >> index 9ffa6bc72cf1..71857c68bbed 100644 >> --- a/drivers/media/platform/qcom/camss/camss-vfe.c >> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c >> @@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line >> *line, u32 sink_code, >> case CAMSS_8280XP: >> case CAMSS_845: >> case CAMSS_8550: >> + case CAMSS_8775P: >> switch (sink_code) { >> case MEDIA_BUS_FMT_YUYV8_1X16: >> { >> @@ -908,7 +909,8 @@ static int vfe_match_clock_names(struct >> vfe_device *vfe, >> return (!strcmp(clock->name, vfe_name) || >> !strcmp(clock->name, vfe_lite_name) || >> - !strcmp(clock->name, "vfe_lite")); >> + !strcmp(clock->name, "vfe_lite") || >> + !strcmp(clock->name, "camnoc_axi")); >> } >> /* >> @@ -1972,6 +1974,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) >> case CAMSS_8280XP: >> case CAMSS_845: >> case CAMSS_8550: >> + case CAMSS_8775P: >> ret = 16; >> break; >> default: >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h >> b/drivers/media/platform/qcom/camss/camss-vfe.h >> index 9dec5bc0d1b1..a9322f4440ae 100644 >> --- a/drivers/media/platform/qcom/camss/camss-vfe.h >> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h >> @@ -243,6 +243,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7; >> extern const struct vfe_hw_ops vfe_ops_4_8; >> extern const struct vfe_hw_ops vfe_ops_170; >> extern const struct vfe_hw_ops vfe_ops_480; >> +extern const struct vfe_hw_ops vfe_ops_690; >> extern const struct vfe_hw_ops vfe_ops_780; >> int vfe_get(struct vfe_device *vfe); >> diff --git a/drivers/media/platform/qcom/camss/camss.c >> b/drivers/media/platform/qcom/camss/camss.c >> index 9458cba1b50f..4df31c89c20c 100644 >> --- a/drivers/media/platform/qcom/camss/camss.c >> +++ b/drivers/media/platform/qcom/camss/camss.c >> @@ -2478,6 +2478,196 @@ static const struct camss_subdev_resources >> csid_res_8775p[] = { >> }, >> }; >> +static const struct camss_subdev_resources vfe_res_8775p[] = { >> + /* VFE0 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb", >> + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", >> + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", >> + "icp_ahb"}, >> + .clock_rate = { >> + { 0 }, >> + { 480000000 }, >> + { 300000000, 400000000 }, >> + { 300000000, 400000000 }, >> + { 0 }, >> + { 0 }, >> + { 0, 80000000 }, >> + { 300000000, 400000000 }, >> + { 400000000 }, >> + { 0 }, >> + }, >> + >> + .reg = { "vfe0" }, >> + .interrupt = { "vfe0" }, >> + .vfe = { >> + .line_num = 3, >> + .is_lite = false, >> + .has_pd = false, >> + .pd_name = NULL, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE1 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb", >> + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", >> + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", >> + "icp_ahb"}, >> + .clock_rate = { >> + { 0 }, >> + { 480000000 }, >> + { 300000000, 400000000 }, >> + { 300000000, 400000000 }, >> + { 0 }, >> + { 0 }, >> + { 0, 80000000 }, >> + { 300000000, 400000000 }, >> + { 400000000 }, >> + { 0 }, >> + }, >> + >> + .reg = { "vfe1" }, >> + .interrupt = { "vfe1" }, >> + .vfe = { >> + .line_num = 3, >> + .is_lite = false, >> + .has_pd = false, >> + .pd_name = NULL, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + >> + /* VFE2 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite0" }, >> + .interrupt = { "vfe-lite0" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE3 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite1" }, >> + .interrupt = { "vfe-lite1" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE4 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite2" }, >> + .interrupt = { "vfe-lite2" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE5 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite3" }, >> + .interrupt = { "vfe-lite3" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE6 (lite) */ >> + { >> + .regulators = {}, >> + >> + .clock = { "cpas_ife_lite", "vfe_lite_ahb", >> + "vfe_lite_csid", "vfe_lite_cphy_rx", >> + "vfe_lite"}, >> + .clock_rate = { >> + { 0, 0, 0, 0 }, >> + { 300000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 400000000, 400000000, 400000000, 400000000 }, >> + { 480000000, 600000000, 600000000, 600000000 }, >> + }, >> + .reg = { "vfe_lite4" }, >> + .interrupt = { "vfe-lite4" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_690, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> +}; >> + >> static const struct resources_icc icc_res_sa8775p[] = { >> { >> .name = "ahb", >> @@ -3469,9 +3659,11 @@ static const struct camss_resources >> sa8775p_resources = { >> .csiphy_res = csiphy_res_8775p, >> .csid_res = csid_res_8775p, >> .csid_wrapper_res = &csid_wrapper_res_sa8775p, >> + .vfe_res = vfe_res_8775p, >> .icc_res = icc_res_sa8775p, >> .csiphy_num = ARRAY_SIZE(csiphy_res_8775p), >> .csid_num = ARRAY_SIZE(csid_res_8775p), >> + .vfe_num = ARRAY_SIZE(vfe_res_8775p), >> .icc_path_num = ARRAY_SIZE(icc_res_sa8775p), >> .link_entities = camss_link_entities >> }; > > There's a pretty superficial difference between 780 and 990 > > git diff drivers/media/platform/qcom/camss/camss-vfe-690.c > drivers/media/platform/qcom/camss/camss-vfe-780.c > > linux-media-qcom-camss/master? > 3c3 > < * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v690 > (SA8755P) > --- > > * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 > (SM8550) > 5c5 > < * Copyright (c) 2025 Qualcomm Technologies, Inc. > --- > > * Copyright (c) 2024 Qualcomm Technologies, Inc. > 15,16c15 > < #define VFE_TOP_CORE_CFG (0x24) > < #define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x480 : 0x400) > --- > > #define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00) > > 19c18 > < #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) > --- > > #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) > 21c20 > < #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xFC) > --- > > #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC) > 46,47c45,46 > < * VFE: > < * 16 = RDI0, 17 = RDI1, 18 = RDI2 > --- > > * Full VFE: > > * 23 = RDI0, 24 = RDI1, 25 = RDI2 > 50c49 > < * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5 > --- > > * 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4 > 52c51 > < #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n)) > --- > > #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) > 61d59 > < writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); > 62a61,62 > > writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); > > > 65c65 > < writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height, > --- > > writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height > >> 8, > 67c67 > < writel(WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF, > --- > > writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), > 71,75c71 > < > < writel(0x0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); > < > < /* TOP CORE CFG */ > < writel(0x600000, vfe->base + VFE_TOP_CORE_CFG); > > What's this for ? > > --- > > writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); > 99c95 > < writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); > --- > > writel((addr >> 8) & 0xFFFFFFFF, vfe->base + > VFE_BUS_WM_IMAGE_ADDR(wm)); > 120c116 > < static const struct camss_video_ops vfe_video_ops_690 = { > --- > > static const struct camss_video_ops vfe_video_ops_780 = { > 127c123 > < vfe->video_ops = vfe_video_ops_690; > --- > > vfe->video_ops = vfe_video_ops_780; > 147c143 > < const struct vfe_hw_ops vfe_ops_690 = { > --- > > const struct vfe_hw_ops vfe_ops_780 = { > > I don't really see much logical difference here to justify all of the > copy/paste code. > > Could you comment on some set of offsets passed in the VFE resources > structure ? > > If not an offset then perhaps a camss-vfe-gen3.c file which contains > the shared code and wrappering that shared code in camss-vfe-690 and > vfe-780 respectively ? > > Actually, I think that's the way to go, for his level of similarity it > should be possible to move the share code 1:1 in many cases to a > shared file. > Agree with your suggestion to move common code to *_gen3.c. Next patch in this series will take care of that. Additionally I will add more info regarding the delta for 'vfe 780' vs 'vfe 690'. Best Regards, Vikram > --- > bod
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index f1d0e9a00220..284f1775f62f 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -18,6 +18,7 @@ qcom-camss-objs += \ camss-vfe-4-8.o \ camss-vfe-17x.o \ camss-vfe-480.o \ + camss-vfe-690.o \ camss-vfe-780.o \ camss-vfe-gen1.o \ camss-vfe.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-690.c b/drivers/media/platform/qcom/camss/camss-vfe-690.c new file mode 100644 index 000000000000..92c92065f65b --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-690.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v690 (SA8755P) + * + * Copyright (c) 2025 Qualcomm Technologies, Inc. + */ + +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/iopoll.h> + +#include "camss.h" +#include "camss-vfe.h" + +#define VFE_TOP_CORE_CFG (0x24) +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x480 : 0x400) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xFC) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) +#define WM_CFG_EN BIT(0) +#define WM_VIR_FRM_EN BIT(1) +#define WM_CFG_MODE BIT(16) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) + +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) + +/* + * Bus client mapping: + * + * VFE: + * 16 = RDI0, 17 = RDI1, 18 = RDI2 + * + * VFE LITE: + * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5 + */ +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n)) + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) +{ + struct v4l2_pix_format_mplane *pix = + &line->video_out.active_fmt.fmt.pix_mp; + + wm = RDI_WM(wm); + + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + /* no clock gating at bus input */ + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel(WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF, + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + + writel(0x0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* TOP CORE CFG */ + writel(0x600000, vfe->base + VFE_TOP_CORE_CFG); + + /* no dropped frames, one irq per frame */ + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); + + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm = RDI_WM(wm); + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm = RDI_WM(wm); + writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); + + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", + wm, addr); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) +{ + int port_id = line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, false); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + int port_id = line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, true); +} + +static const struct camss_video_ops vfe_video_ops_690 = { + .queue_buffer = vfe_queue_buffer_v2, + .flush_buffers = vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops = vfe_video_ops_690; +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + vfe_isr_reset_ack(vfe); +} + +static irqreturn_t vfe_isr(int irq, void *dev) +{ + /* nop */ + return IRQ_HANDLED; +} + +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +const struct vfe_hw_ops vfe_ops_690 = { + .global_reset = vfe_global_reset, + .hw_version = vfe_hw_version, + .isr = vfe_isr, + .pm_domain_off = vfe_pm_domain_off, + .pm_domain_on = vfe_pm_domain_on, + .reg_update = vfe_reg_update, + .reg_update_clear = vfe_reg_update_clear, + .subdev_init = vfe_subdev_init, + .vfe_disable = vfe_disable, + .vfe_enable = vfe_enable_v2, + .vfe_halt = vfe_halt, + .vfe_wm_start = vfe_wm_start, + .vfe_wm_stop = vfe_wm_stop, + .vfe_buf_done = vfe_buf_done, + .vfe_wm_update = vfe_wm_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 9ffa6bc72cf1..71857c68bbed 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_8280XP: case CAMSS_845: case CAMSS_8550: + case CAMSS_8775P: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -908,7 +909,8 @@ static int vfe_match_clock_names(struct vfe_device *vfe, return (!strcmp(clock->name, vfe_name) || !strcmp(clock->name, vfe_lite_name) || - !strcmp(clock->name, "vfe_lite")); + !strcmp(clock->name, "vfe_lite") || + !strcmp(clock->name, "camnoc_axi")); } /* @@ -1972,6 +1974,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_8280XP: case CAMSS_845: case CAMSS_8550: + case CAMSS_8775P: ret = 16; break; default: diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index 9dec5bc0d1b1..a9322f4440ae 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -243,6 +243,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7; extern const struct vfe_hw_ops vfe_ops_4_8; extern const struct vfe_hw_ops vfe_ops_170; extern const struct vfe_hw_ops vfe_ops_480; +extern const struct vfe_hw_ops vfe_ops_690; extern const struct vfe_hw_ops vfe_ops_780; int vfe_get(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 9458cba1b50f..4df31c89c20c 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2478,6 +2478,196 @@ static const struct camss_subdev_resources csid_res_8775p[] = { }, }; +static const struct camss_subdev_resources vfe_res_8775p[] = { + /* VFE0 */ + { + .regulators = {}, + + .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb", + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", + "icp_ahb"}, + .clock_rate = { + { 0 }, + { 480000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 0 }, + { 0 }, + { 0, 80000000 }, + { 300000000, 400000000 }, + { 400000000 }, + { 0 }, + }, + + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .has_pd = false, + .pd_name = NULL, + .hw_ops = &vfe_ops_690, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators = {}, + + .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb", + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", + "icp_ahb"}, + .clock_rate = { + { 0 }, + { 480000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 0 }, + { 0 }, + { 0, 80000000 }, + { 300000000, 400000000 }, + { 400000000 }, + { 0 }, + }, + + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .has_pd = false, + .pd_name = NULL, + .hw_ops = &vfe_ops_690, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + + /* VFE2 (lite) */ + { + .regulators = {}, + + .clock = { "cpas_ife_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate = { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe-lite0" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_690, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE3 (lite) */ + { + .regulators = {}, + + .clock = { "cpas_ife_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate = { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe-lite1" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_690, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE4 (lite) */ + { + .regulators = {}, + + .clock = { "cpas_ife_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate = { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg = { "vfe_lite2" }, + .interrupt = { "vfe-lite2" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_690, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE5 (lite) */ + { + .regulators = {}, + + .clock = { "cpas_ife_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate = { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg = { "vfe_lite3" }, + .interrupt = { "vfe-lite3" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_690, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE6 (lite) */ + { + .regulators = {}, + + .clock = { "cpas_ife_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate = { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg = { "vfe_lite4" }, + .interrupt = { "vfe-lite4" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_690, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, +}; + static const struct resources_icc icc_res_sa8775p[] = { { .name = "ahb", @@ -3469,9 +3659,11 @@ static const struct camss_resources sa8775p_resources = { .csiphy_res = csiphy_res_8775p, .csid_res = csid_res_8775p, .csid_wrapper_res = &csid_wrapper_res_sa8775p, + .vfe_res = vfe_res_8775p, .icc_res = icc_res_sa8775p, .csiphy_num = ARRAY_SIZE(csiphy_res_8775p), .csid_num = ARRAY_SIZE(csid_res_8775p), + .vfe_num = ARRAY_SIZE(vfe_res_8775p), .icc_path_num = ARRAY_SIZE(icc_res_sa8775p), .link_entities = camss_link_entities };