| Message ID | 20250220070114.15015-2-bo.kong@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add MTK AIE Driver For MT8188 | expand |
On Thu, Feb 20, 2025 at 02:59:50PM +0800, bo.kong wrote: > From: Bo Kong <Bo.Kong@mediatek.com> > > Add YAML device tree bindings for MT8188 AIE. > > Signed-off-by: Bo Kong <Bo.Kong@mediatek.com> > --- > Changes in v4: > 1. Remove address-cells and size-cells > 2. Remove larb12 related content > 3. Update id content > > Changes in v3: > None > > Changes in v2: > 1. Fix coding style > --- > .../bindings/media/mediatek,mt8188-aie.yaml | 90 +++++++++++++++++++ > 1 file changed, 90 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml > new file mode 100644 > index 000000000000..232b5afc2ad3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8188-aie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: The AI Engine Unit of MediaTek Camera System > + > +maintainers: > + - Bo Kong <bo.kong@mediatek.com> > + > +description: > + AIE(AI Engine) is one of the units in mt8188 ISP which > + provides hardware accelerated face detection function, > + it can detect different sizes of faces in a raw image. Wrap lines at 80 char. > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8188-aie > + > + reg: > + maxItems: 1 > + description: Physical base address and length of the register space. Drop description. That's every 'reg' entry. > + > + interrupts: > + maxItems: 1 > + > + mediatek,larb: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Must contain the local arbiters in the current SoCs, see > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml > + for details. > + > + iommus: > + maxItems: 4 > + description: > + Points to the respective IOMMU block with master port as argument, see > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. > + Ports are according to the HW. It's not really clear what the 4 entries are. Like any other property, the order should be defined. > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: clock for imgsys main ipe > + - description: clock for ipe fdvt > + - description: clock for ipe top > + > + clock-names: > + items: > + - const: img_ipe > + - const: ipe_fdvt > + - const: ipe_top > + > +required: > + - compatible > + - reg > + - interrupts > + - iommus > + - power-domains > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h> > + #include <dt-bindings/power/mediatek,mt8188-power.h> > + #include <dt-bindings/clock/mediatek,mt8188-clk.h> > + aie@15310000 { > + compatible = "mediatek,mt8188-aie"; > + reg = <0x15310000 0x1000>; > + interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH 0>; > + iommus = <&vpp_iommu M4U_PORT_L12_FDVT_RDA_0>, > + <&vpp_iommu M4U_PORT_L12_FDVT_RDB_0>, > + <&vpp_iommu M4U_PORT_L12_FDVT_WRA_0>, > + <&vpp_iommu M4U_PORT_L12_FDVT_WRB_0>; > + power-domains = <&spm MT8188_POWER_DOMAIN_IPE>; > + clocks = <&imgsys CLK_IMGSYS_MAIN_IPE>, > + <&ipesys CLK_IPE_FDVT>, > + <&ipesys CLK_IPESYS_TOP>; > + clock-names = "img_ipe", > + "ipe_fdvt", > + "ipe_top"; > + }; > -- > 2.45.2 >
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml new file mode 100644 index 000000000000..232b5afc2ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8188-aie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The AI Engine Unit of MediaTek Camera System + +maintainers: + - Bo Kong <bo.kong@mediatek.com> + +description: + AIE(AI Engine) is one of the units in mt8188 ISP which + provides hardware accelerated face detection function, + it can detect different sizes of faces in a raw image. + +properties: + compatible: + items: + - const: mediatek,mt8188-aie + + reg: + maxItems: 1 + description: Physical base address and length of the register space. + + interrupts: + maxItems: 1 + + mediatek,larb: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Must contain the local arbiters in the current SoCs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml + for details. + + iommus: + maxItems: 4 + description: + Points to the respective IOMMU block with master port as argument, see + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + Ports are according to the HW. + + power-domains: + maxItems: 1 + + clocks: + items: + - description: clock for imgsys main ipe + - description: clock for ipe fdvt + - description: clock for ipe top + + clock-names: + items: + - const: img_ipe + - const: ipe_fdvt + - const: ipe_top + +required: + - compatible + - reg + - interrupts + - iommus + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h> + #include <dt-bindings/power/mediatek,mt8188-power.h> + #include <dt-bindings/clock/mediatek,mt8188-clk.h> + aie@15310000 { + compatible = "mediatek,mt8188-aie"; + reg = <0x15310000 0x1000>; + interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L12_FDVT_RDA_0>, + <&vpp_iommu M4U_PORT_L12_FDVT_RDB_0>, + <&vpp_iommu M4U_PORT_L12_FDVT_WRA_0>, + <&vpp_iommu M4U_PORT_L12_FDVT_WRB_0>; + power-domains = <&spm MT8188_POWER_DOMAIN_IPE>; + clocks = <&imgsys CLK_IMGSYS_MAIN_IPE>, + <&ipesys CLK_IPE_FDVT>, + <&ipesys CLK_IPESYS_TOP>; + clock-names = "img_ipe", + "ipe_fdvt", + "ipe_top"; + };