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Wed, 05 Mar 2025 11:05:32 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391241bd151sm2045218f8f.21.2025.03.05.11.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 11:05:31 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:24 +0100 Subject: [PATCH v2 6/7] media: platform: qcom/iris: add support for vpu33 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-topic-sm8x50-iris-v10-v2-6-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The IRIS acceleration found in the SM8650 platforms uses the vpu33 hardware version, and requires a slighly different reset and power off sequences in order to properly get out of runtime suspend. Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 144 +++++++++++++++++++-- drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 +- drivers/media/platform/qcom/iris/iris_vpu_common.h | 3 + 3 files changed, 137 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 95f362633c95b101ecfda6480c4c0b73416bd00c..109f663d031ab5f5ee8b58eb2a781eb27d2675aa 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -4,11 +4,13 @@ */ #include +#include #include "iris_instance.h" #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" +#define AON_BASE_OFFS 0x000E0000 #define AON_MVP_NOC_RESET 0x0001F000 #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) @@ -25,7 +27,16 @@ #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) -static bool iris_vpu3_hw_power_collapsed(struct iris_core *core) +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) + +#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) +#define SW_RESET BIT(0) +#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) +#define NOC_HALT BIT(0) +#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) + +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) { u32 value, pwr_status; @@ -35,13 +46,13 @@ static bool iris_vpu3_hw_power_collapsed(struct iris_core *core) return pwr_status ? false : true; } -static void iris_vpu3_power_off_hardware(struct iris_core *core) +static int iris_vpu3x_power_off_hardware_begin(struct iris_core *core) { u32 reg_val = 0, value, i; int ret; - if (iris_vpu3_hw_power_collapsed(core)) - goto disable_power; + if (iris_vpu3x_hw_power_collapsed(core)) + return 1; dev_err(core->dev, "video hw is power on\n"); @@ -53,9 +64,29 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i, reg_val, reg_val & 0x400000, 2000, 20000); if (ret) - goto disable_power; + return ret; } + return 0; +} + +static void iris_vpu3x_power_off_hardware_end(struct iris_core *core) +{ + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); +} + +static void iris_vpu3_power_off_hardware(struct iris_core *core) +{ + u32 reg_val = 0; + int ret; + + ret = iris_vpu3x_power_off_hardware_begin(core); + if (ret) + goto disable_power; + writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, @@ -70,16 +101,100 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) if (ret) goto disable_power; - writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, - core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); - writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); - writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + iris_vpu3x_power_off_hardware_end(core); + +disable_power: + iris_vpu_power_off_hw(core); +} + +static void iris_vpu33_power_off_hardware(struct iris_core *core) +{ + u32 reg_val = 0; + int ret; + + ret = iris_vpu3x_power_off_hardware_begin(core); + if (ret) + goto disable_power; + + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, + reg_val, reg_val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ + writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + iris_vpu3x_power_off_hardware_end(core); disable_power: iris_vpu_power_off_hw(core); } -static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t data_size) +static int iris_vpu33_power_off_controller(struct iris_core *core) +{ + u32 xo_rst_tbl_size = core->iris_platform_data->controller_rst_tbl_size; + u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; + u32 val = 0; + int ret; + + iris_vpu_power_off_controller_begin(core); + + ret = iris_vpu_power_off_controller_end(core); + if (ret) + goto disable_power; + + reset_control_bulk_reset(clk_rst_tbl_size, core->resets); + + /* Disable MVP NoC clock */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val |= NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + /* enable MVP NoC reset */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val |= SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + /* poll AON spare register bit0 to become zero with 50ms timeout */ + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_SPARE, + val, (val & BIT(0)) == 0, 1000, 50000); + if (ret) + goto disable_power; + + /* enable bit(1) to avoid cvp noc xo reset */ + val = readl(core->reg_base + AON_WRAPPER_SPARE); + val |= BIT(1); + writel(val, core->reg_base + AON_WRAPPER_SPARE); + + reset_control_bulk_assert(xo_rst_tbl_size, core->controller_resets); + + /* De-assert MVP NoC reset */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val &= ~SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + usleep_range(80, 100); + + reset_control_bulk_deassert(xo_rst_tbl_size, core->controller_resets); + + /* reset AON spare register */ + writel(0, core->reg_base + AON_WRAPPER_SPARE); + + /* Enable MVP NoC clock */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val &= ~NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + +disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + + return 0; +} + +static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t data_size) { struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; struct v4l2_format *inp_f = inst->fmt_src; @@ -117,8 +232,13 @@ static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t data_siz } const struct vpu_ops iris_vpu3_ops = { - .reset_controller = iris_vpu_reset_controller, .power_off_hw = iris_vpu3_power_off_hardware, .power_off_controller = iris_vpu_power_off_controller, - .calc_freq = iris_vpu3_calculate_frequency, + .calc_freq = iris_vpu3x_calculate_frequency, +}; + +const struct vpu_ops iris_vpu33_ops = { + .power_off_hw = iris_vpu33_power_off_hardware, + .power_off_controller = iris_vpu33_power_off_controller, + .calc_freq = iris_vpu3x_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 3b3e1ca1e42183561ee78c89f50946fd0cc3c3ab..43c62e2ee593146b8e3448e8c7cab44ef1a15bf2 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -211,12 +211,12 @@ int iris_vpu_prepare_pc(struct iris_core *core) return -EAGAIN; } -static void iris_vpu_power_off_controller_begin(struct iris_core *core) +void iris_vpu_power_off_controller_begin(struct iris_core *core) { writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); } -static int iris_vpu_power_off_controller_end(struct iris_core *core) +int iris_vpu_power_off_controller_end(struct iris_core *core) { u32 val = 0; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index f8965661c602f990d5a7057565f79df4112d097e..4af3cb0d44e00be498fc7ba648c68f1ef2cb0f20 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,6 +10,7 @@ struct iris_core; extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu33_ops; struct vpu_ops { void (*power_off_hw)(struct iris_core *core); @@ -23,6 +24,8 @@ void iris_vpu_clear_interrupt(struct iris_core *core); int iris_vpu_watchdog(struct iris_core *core, u32 intr_status); int iris_vpu_prepare_pc(struct iris_core *core); int iris_vpu_power_on(struct iris_core *core); +void iris_vpu_power_off_controller_begin(struct iris_core *core); +int iris_vpu_power_off_controller_end(struct iris_core *core); int iris_vpu_power_off_controller(struct iris_core *core); void iris_vpu_power_off_hw(struct iris_core *core); void iris_vpu_power_off(struct iris_core *core);