From patchwork Wed Oct 16 10:22:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 13838166 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63D612071F6; Wed, 16 Oct 2024 10:22:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729074158; cv=none; b=MZk0g0gm4zoAJGSk9YyNrG5Q/x1AJCEU1TZ09XcQLiSkWHL/bv9ixJ2aYDO3iAiLEfRQKJrzagAaHErMOuXyVPgkZwjnkF6SY2PgGpyLLUMXRImig0rbTep5aXYybkcq01UkrlATFaVX0X26CvFTi9qG3ceaS8Lu8typnjyTNpM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729074158; c=relaxed/simple; bh=vq7QJpYiMutw0B1hm8O24dEVpiMZEcoq2f2zZUsJPKk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ogPno82wIrTFns9B7mE0AWGU4JbsiH4Z6roIVESAnTu4ZoKyxVnBDfYLFQv9o1eCN7S51KCzxsZ4xpkiDVVj8FOrXZQEkv0Dd/0KX3cJM1W0S8x/34SmfU+KXogTIxhiqozq6pUT8QOD0z6h0fFfjsgs15rWUA+NM2IwTfhT79Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tqetwn/j; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tqetwn/j" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DFFBAC4CED8; Wed, 16 Oct 2024 10:22:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729074157; bh=vq7QJpYiMutw0B1hm8O24dEVpiMZEcoq2f2zZUsJPKk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tqetwn/juQJdGucRqIq2PBHKkF6EhDe0jorxR1wAuGRT8x4mtvPN7XbotVG9V6Zas SDr1HPBnZtzyBTAfPvF6dzNlnlOUQeNR0QY7eTVU9dX6B6bxJL/o/QNNofN5shoixS NuD1fCyAGjZqaeaabqW7arDwj2rDYrF+cRr26k6aa4oWL/SYAgYwyR3HqSNPH9T+Z/ 4ERp9I5ylUvFxFLLXi0yR0nqLIIk6xGOv8zeW0mdcTd3/46kyg8jMvVduR4jbDYU7J rucX1GHCD7hafdpkKQFfigEkirt+8Z3apXboak1SqQJfOh18mvxcWcDRtqC0K3JPmb q8Z1SBAdukJMA== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1t11Ap-00000004Ymt-2ZRN; Wed, 16 Oct 2024 12:22:35 +0200 From: Mauro Carvalho Chehab To: Cc: Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_H?= =?utf-8?q?a=C5=82asa?= , Mauro Carvalho Chehab , Sakari Ailus , linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH 08/13] media: ar0521: don't overflow when checking PLL values Date: Wed, 16 Oct 2024 12:22:24 +0200 Message-ID: <39b23d468eea2714a24a94cb6c20aef5aff492e6.1729074076.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab The PLL checks are comparing 64 bit integers with 32 bit ones. Depending on the values of the variables, this may underflow. Fix it ensuring that both sides of the expression are u64. Fixes: 852b50aeed15 ("media: On Semi AR0521 sensor driver") Cc: stable@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab Acked-by: Sakari Ailus --- drivers/media/i2c/ar0521.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ar0521.c b/drivers/media/i2c/ar0521.c index fc27238dd4d3..24873149096c 100644 --- a/drivers/media/i2c/ar0521.c +++ b/drivers/media/i2c/ar0521.c @@ -255,10 +255,10 @@ static u32 calc_pll(struct ar0521_dev *sensor, u32 freq, u16 *pre_ptr, u16 *mult continue; /* Minimum value */ if (new_mult > 254) break; /* Maximum, larger pre won't work either */ - if (sensor->extclk_freq * (u64)new_mult < AR0521_PLL_MIN * + if (sensor->extclk_freq * (u64)new_mult < (u64)AR0521_PLL_MIN * new_pre) continue; - if (sensor->extclk_freq * (u64)new_mult > AR0521_PLL_MAX * + if (sensor->extclk_freq * (u64)new_mult > (u64)AR0521_PLL_MAX * new_pre) break; /* Larger pre won't work either */ new_pll = div64_round_up(sensor->extclk_freq * (u64)new_mult,