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Tue, 20 Jul 2021 01:44:47 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 12/13] firmware: imx: scu-pd: imx8q: add vpu mu resources Date: Tue, 20 Jul 2021 09:43:31 +0800 Message-Id: <4b2b07fd3000e2a7235049e033dc5887942fc793.1626743758.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: X-ClientProxiedBy: SG2PR06CA0232.apcprd06.prod.outlook.com (2603:1096:4:ac::16) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR06CA0232.apcprd06.prod.outlook.com (2603:1096:4:ac::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 812MRsu5xGTAk5JGGK31kQsMjfm84yNcsocSOQU8L/zRwjlTf+8gJ/clfrVIGhNeX6dXA0kJXKFxcjeRIjYbFuxA1QSrpQ2cF3BnVeesLFzI8Njfq5IoI+NPRiZC++2l/b9w1HGMdsSl8OKzTLk0Xt8qLVFEslwQdkySiKW2zMHC/BvRTJP4/1wS4wpAmhQfTFn0u5Q/aoxWTTvyZ0GoG9IZo7oAA/eBht+txz0yw0wJ/EVeFzofvAjxGBR9bWsTDB2/niSTzc/OmAWsDIbYuRKFBKJlSEPozf2qEViNm8kN6fEfay2IfYBUOnNj4a2Tq60dIsF2jAlvkHYQCm/EJDXnljwF5klxbuoOo2MHPvq4yY2u1oZU42fsmy7Ig6zdDWI7KhXxvGuFkzL0FD3IE/2eQZyHXQrwVesAINVOYYYLNg+uRdH7Cv7pQ6BiTI62DEjX0md1BdwEaCvsF8rymoMj+HTg/F8a66ssNCCjzkMEzn1rgYwbppI4ABcvdj05NQpcJ6uzDZHceVcgzgRFPfQhMmZXpz17ddLS9KQVdaOa3xemEuDalqr6Ob6zvlL0T5vhT51yWwzTefGtCtKkoYIEYaajP7RtDVxudg4zJWGIirtLgst5KaqhCXVPgxMxcLbUTIFFjEb2guGctjKGjVpUWi60oT/UxNgCqoe0yIh2gVvhl3EbcjfjJdObBWrQ3XX2WY8MHU+lt76KOfvY6x6Ph8QiJNIARgA9CN2nT6kKxSjRsDbke4Q1eNvmYVTJas0LbFMofLT8wEkcTPDfC3Fw46bzMrqKMkyCsln6EMDlifjB+ZHnIncNbE7B/XHStz0GE7ZVPmv5jUGAi/0R8o1u7bGT/SNrBAmUJbNw9xVxV3m1LAixRUVQKTQwagdKzrZuiS4PDPcJ/eA1cTVecfXcX9YrW8VtSWCBesvDgx3XXwPDUA7YxmIVTkm/mZZhu7JQnfVmhStqTZFWPfflSwMXh+qpgupEUe4WGyu049Vi46VRnlrWcQU53rQ3i9VR+d+uxLAeJErDacwhULCGzAF6hsEVGrz8D7sc2NR10xowCKkDeGsw6MKQihCBwmlpomxyWrOJHWmLTiGz1DtKHTsiks0SwdIkRTD5woWReHEeSdr6OkfoqYXc7hcpBDRxQGNu4u2r5sXWGT+kyCEZinZCcXgHhZfwsHa4xKwvgLdkaGO6OctOoF2TZX/K33ztZJOHYbOTqRGhBC4Rb82y7KCRM0iwcfukJ7otSDVdzI9yQyli1jiP5TLN3LDcxYt2YFaSX8pHXoAmLGy7so4sGM8eCTFI5YgMUaSAQgSQn8cmWNd4ounE7B4utBdMCYRr X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 13a20045-6c63-4fff-db1b-08d94b1ff4ca X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2021 01:44:47.5748 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 04xTMAkA+SQDSs7C9xdZObgXIn+Qap75BU7OuqO2BuR55CoZbgrDPAzh5y1GtmCRhgmXJUGjlUeZ3X11CD2HEA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3813 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org the vpu core depends on the mu resources. if they're missed, the vpu can't work. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index af3d6d9ead28..48bcc9355a7c 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -145,6 +145,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },