From patchwork Fri Dec 31 11:37:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Igor M. Liplianin" X-Patchwork-Id: 442861 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p019Vwvn010546 for ; Sat, 1 Jan 2011 09:31:59 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751762Ab1AAJbi (ORCPT ); Sat, 1 Jan 2011 04:31:38 -0500 Received: from mail-ew0-f46.google.com ([209.85.215.46]:61142 "EHLO mail-ew0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751296Ab1AAJbh (ORCPT ); Sat, 1 Jan 2011 04:31:37 -0500 Received: by ewy5 with SMTP id 5so5608255ewy.19 for ; Sat, 01 Jan 2011 01:31:36 -0800 (PST) Received: by 10.213.14.146 with SMTP id g18mr15652717eba.2.1293874296123; Sat, 01 Jan 2011 01:31:36 -0800 (PST) Received: from useri.localnet ([93.125.74.3]) by mx.google.com with ESMTPS id u1sm12964950eeh.4.2011.01.01.01.31.34 (version=SSLv3 cipher=RC4-MD5); Sat, 01 Jan 2011 01:31:35 -0800 (PST) Message-ID: <4d1ef477.017b0e0a.28f5.0d41@mx.google.com> From: Abylay Ospan Date: Fri, 31 Dec 2010 13:37:00 +0200 Subject: [PATCH 08/18] cx23885: Altera FPGA CI interface reworked. To: , , Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Sat, 01 Jan 2011 09:31:59 +0000 (UTC) diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c index 6c144f7..53c2b6d 100644 --- a/drivers/media/video/cx23885/cx23885-dvb.c +++ b/drivers/media/video/cx23885/cx23885-dvb.c @@ -620,29 +620,29 @@ int netup_altera_fpga_rw(void *device, int flag, int data, int read) { struct cx23885_dev *dev = (struct cx23885_dev *)device; unsigned long timeout = jiffies + msecs_to_jiffies(1); - int mem = 0; + uint32_t mem = 0; - cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS); + mem = cx_read(MC417_RWD); if (read) cx_set(MC417_OEN, ALT_DATA); else { cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */ - mem = cx_read(MC417_RWD); mem &= ~ALT_DATA; mem |= (data & ALT_DATA); - cx_write(MC417_RWD, mem); } if (flag) - cx_set(MC417_RWD, ALT_AD_RG);/* ADDR */ + mem |= ALT_AD_RG; else - cx_clear(MC417_RWD, ALT_AD_RG);/* VAL */ + mem &= ~ALT_AD_RG; - cx_clear(MC417_RWD, ALT_CS);/* ~CS */ + mem &= ~ALT_CS; if (read) - cx_clear(MC417_RWD, ALT_RD); + mem = (mem & ~ALT_RD) | ALT_WR; else - cx_clear(MC417_RWD, ALT_WR); + mem = (mem & ~ALT_WR) | ALT_RD; + + cx_write(MC417_RWD, mem); /* start RW cycle */ for (;;) { mem = cx_read(MC417_RWD);