| Message ID | 501C23D7.3020307@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Sylwester, On Fri, 2012-08-03 at 21:17 +0200, Sylwester Nawrocki wrote: > Hi Mike, > > On 08/02/2012 02:48 PM, Mike Dyer wrote: > > Hi All, > > > > I'm using the S5PV210 camera IF and capturing BT656 video from a TVP5150 > > video decoder. > > > > I notice that the capture driver ignores the field interlace flags > > reported by the 'sensor' and always uses 'V4L2_FIELD_NONE'. It also > > seems each field ends up in it's own frame, using only half the height. > > s5p-fimc driver doesn't support the interlaced video capture, as we had > no such use case yet. Patches adding it are welcome. > > > What would need to be done to store both fields in a single frame, for > > example in a V4L2_FIELD_INTERLACE_TB/BT format? > > Firstly, it would good to figure out FIMC register settings that would > allow storing both fields in a single frame. I _suspect_ it's as simple > as setting CAM_INTERLACE bit in CIGCTRL register. Have you perhaps tried > it already ? > > For a quick test a patch as below might be sufficient. > > > diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c > index 1fc4ce8..19afa1a 100644 > --- a/drivers/media/video/s5p-fimc/fimc-reg.c > +++ b/drivers/media/video/s5p-fimc/fimc-reg.c > @@ -576,6 +576,8 @@ int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, > if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW) > cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD; > > + cfg |= FIMC_REG_CIGCTRL_INTERLACE; > + > writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); > > return 0; > > > -- > > Thanks, > Sylwester I have indeed tried setting that, but with no effect. However, checking through the datasheet for the FIMC I discovered a DMA output (CIOCTRL) register bit called 'Weave_Out'. The description is: "Even and Odd fields can be weaved together and combined to form a complete progressive frame by hardware. This field is useful for interlace DMA output mode (Interlace_out or CAM_INTERLACE). Even field address (1st frame start address) is used weave address. Odd fields address (2nd frame start address) is ignored." This does produce full sized frames, but I still seem to only be getting one field per frame, with a blank line inserted between each real line. Setting both interlace and weave doesn't seem to help. So, something still missing... I wonder if the irq handler is getting called for each field, maybe we need to wait for two interrupts before dequeing the frame? Cheers, Mike -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 08/03/2012 10:01 PM, Mike Dyer wrote: > I have indeed tried setting that, but with no effect. However, checking > through the datasheet for the FIMC I discovered a DMA output (CIOCTRL) > register bit called 'Weave_Out'. The description is: > > "Even and Odd fields can be weaved together and combined to form a > complete progressive frame by hardware. This field is useful for > interlace DMA output mode (Interlace_out or CAM_INTERLACE). Even field > address (1st frame start address) is used weave address. Odd fields > address (2nd frame start address) is ignored." > > This does produce full sized frames, but I still seem to only be getting > one field per frame, with a blank line inserted between each real line. > Setting both interlace and weave doesn't seem to help. So, something > still missing... > > I wonder if the irq handler is getting called for each field, maybe we > need to wait for two interrupts before dequeing the frame? Hmm, might be worth to try. But I'm wondering if the output DMA handling doesn't need to be reworked for that. According to the datasheet (Figure 2-20 Frame Buffer Control), even fields are written to DMA buffer with even index (e.g. 0) and odd fields are written to DMA buffer with odd index (e.g. 1). So possibly, if we set same address at two DMA buffer start address registers (e.g. FIMC_REG_CIOYSA(0), FIMC_REG_CIOYSA(1)) then even and odd frame will be written to proper memory location ? This might not be very difficult to implement. -- Regards, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c index 1fc4ce8..19afa1a 100644 --- a/drivers/media/video/s5p-fimc/fimc-reg.c +++ b/drivers/media/video/s5p-fimc/fimc-reg.c @@ -576,6 +576,8 @@ int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW) cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD; + cfg |= FIMC_REG_CIGCTRL_INTERLACE; + writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); return 0;