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Tue, 20 Jul 2021 01:44:00 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 01/13] dt-bindings: media: imx8q: add imx video codec bindings Date: Tue, 20 Jul 2021 09:43:20 +0800 Message-Id: <5032168eca16a277cc8ba9e951073a37089c0eec.1626743758.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: X-ClientProxiedBy: SG2PR06CA0232.apcprd06.prod.outlook.com (2603:1096:4:ac::16) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR06CA0232.apcprd06.prod.outlook.com (2603:1096:4:ac::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rOuWIGDzmKOd376f5H9ZersSNhVthAzZ+H6Xz2NjtTYOJs5sm4QnGQ3c+j+ptQVY6c/UBZEmWyyaiIGSwoUXbw6V60NDlwCnFja+wjYjmDCtSIrKT4PpB6n0/wdMZ8fUnbXovuVVWn16XP+Ezlhb1VeuvIyw5aAuX0UTOzV5Mep1lYyBUDX1uWpa6GzawrUrd66ITgiamuIwW6PLKOHEQKJo3MonLBXSf0xiwb58CjrNX+O8M7nvKbH27i9Ko8dhW2qQA1czmc6IQCgaTTMYbWpn3XSqdqLOnzNXdNVrdaye68PQ1Oq6tYSb6/3ufBU8EXZYjrlf1A2ZQjk9wMWrQGDKfCtXQY+ihFWSsC+IkE+nCLcrCpU3SgfX1f7cXsr7MfpVZtaVdgheI900dHLS1QHuWFwa+BatyufqB2MtFm2ycpyamkSXBa6fcyIFN825ZQ0uOGJ6licRRG6KvAV4vNT7cKcKuFW36XTYNo+4X0nwOgY9riOCyPZbKRBeM0AK45CxU+yQuJLgHnzcvLEvR2PW42JTHywjKT4q2pzrIEpDr8p2g/6ZPFOUWEz6qu15W/C/++yqAJ7VreNt6a64m4LPVfDIBWjoIzU+1Lfn2ZDC6dWpuSnSZWu58nS2FM1ujD5qpjnhV+ypNf5XY40W+KMlcJOyaB+j6wj3fqdY97jReAehQvF14Hgov4aFtRMQfAm6WRXVfgf5wbuYjlKer5vSELVknjUdHuZYc6/WE8ZJOtg66q7MvxK/iYpgj8kaNfq5fmNDl9NxFGPlF6y9I/p3BDpqJ1iTX75zv68mEg0o8alkcZxo3+zj8LWVe5a9QVIHHzDKeVQeSk37MkQQ/SoQU8pGq5J0Ft9k5FYY+Gdq1ZLVq/NE4UeVuGx+aCXXJ4eUl+OR8zrHO2eA83Rib3AcOG4LG2oc3UA82zIBY70heoFmUBjiSgvY2U1rvIgBgA/gyGJtp3MYBvosolH/2HLq8brDmX10k41Bl4omBrCsb98q2V2NSbtACv5opCRC3pyBeROD4nJCpEiBOFaZ+36HlJw1W61oE9E6/SSclowpgUc6DmhKssRtaoNuLBLf2Ukmu1ljZ5xQ7916UvB7ZH3kLOHAV/KFCDzVWeI6tFTQXwLL4lGPa8uloDKGiFRxKWG4RfqctI40NLy4W4aOzOR0LRR2gHKPymkrXfHHBHsQMZ+YZM77Uajtw8IocVCGTD89tECmdXYnhvJH+APozlpk3GwS1z0+c1ie6nYJzfjlae8lwe3QbzSiug2qVhDXyXB0OdJeC7+W+0HI6D71WYyPr6vXnyBkYa3DhMMgOd2xPludiyKtegxpHZAR0vao X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6ebb41e1-6279-4db3-3fc3-08d94b1fd8fd X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2021 01:44:00.8169 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LVM01SgF+yqpP3RTH4GgTyM0vLEjhZ6FzAA47owVBJnprX94USPG+fpHnRGVV2NHcGP+DuYI5DJa1iumXKhPLg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3813 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add devicetree binding documentation for IMX8Q Video Processing Unit IP Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../bindings/media/nxp,imx8q-vpu.yaml | 178 ++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml new file mode 100644 index 000000000000..337c9bf2395f --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8Q video encode and decode accelerators + +maintainers: + - Ming Qian + - Shijie Qin + +description: |- + The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present + on NXP i.MX8Q SoCs. + +properties: + $nodename: + pattern: "^vpu@[0-9a-f]+$" + + compatible: + oneOf: + - const: nxp,imx8qm-vpu + - const: nxp,imx8qxp-vpu + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^mailbox@[0-9a-f]+$": + description: + Each vpu encoder or decoder correspond a MU, which used for communication + between driver and firmware. Implement via mailbox on driver. + $ref: ../mailbox/fsl,mu.yaml# + + + "^vpu_core@[0-9a-f]+$": + description: + Each core correspond a decoder or encoder, need to configure them + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC + has one decoder and one encoder. + type: object + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + items: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + maxItems: 1 + + memory-region: + description: + Phandle to the reserved memory nodes to be associated with the + remoteproc device. The reserved memory nodes should be carveout nodes, + and should be defined as per the bindings in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + items: + - description: region reserved for firmware image sections. + - description: region used for RPC shared memory between firmware and + driver. + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - memory-region + + additionalProperties: false + +required: + - compatible + - reg + - power-domains + +additionalProperties: false + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_core@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + }; + + vpu_core1: vpu_core@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + }; + + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + }; + }; + +...