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Fri, 15 Oct 2021 08:22:53 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v11 01/13] dt-bindings: media: amphion: add amphion video codec bindings Date: Fri, 15 Oct 2021 16:21:50 +0800 Message-Id: <74554b65b3776c1dffb738e37e3fc15d17b37b6a.1634282966.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: References: X-ClientProxiedBy: SI2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:4:194::13) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SI2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:4:194::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yApiFLoGCWcoNy7z/bAr++vEUURS8bDE4T4HdNhB7ZKuASwADLRYN8pMnvaDUvET0L8X6IhkL0QzXlES1yRV2l+4G+xufBCeB+51Uk8wV2NfAJCyDdy9JrFdhwpH6IMJB7g6ONeKr3umIgHnWwYQoTXxwXr5h3oPIkoUz+4GV2bmAg47XBHdSzjPKAce3Yo6PJzoTpRlkx2pc0CAldEXfsyxEC7R/NIb8PnXKkzlblGYop4xXHEujA1inWiHVD5eWCGUa2BZtTngUZQhv7+b+FwPKtzFRVQDx4qsuv5Xsg090e11GO9CBvTplm2UVywV98AMLvxlGn3x8qfezV31N+Sv5q2HFu44UWkFMe0uXlj5MKl9nGdaP+zMHT9/z07pjJhXgw+P1U/tHGmjEiMYNyZSUh/yKpUK1jgue0FFgHX6MzM6pkBnKz4QqktBTFoFStF7Dxzh6tmt4AOaOLnEIKoUpFbWNdTXHUpusfgW9DnjWz83biML0hB67d6sp0RtaD8AmGBNsECk9kNf3TloytsHUs+dyw7yK1er7snJ3fmvb3+9hw+IQJMVIcUAHp8lVBj4KXGnvxSXCDWaz6ADQyUavFgwYJOlUeTGOPucvvagQD1uI1EtcTY8mHSq9+XadBC4PlW8UwIqBD1UKeUVsm3DGWPT8RaRMVQsRAbNjwGyo8ZGc1vGG5y9hX6h315hG5myRtclJo59DH47LFDjb49sZel9TZHw8iuNE6GtgVfdak/rdC4lg8UjiRqjlxgLWd9iXMxZbIQvr58i3MEyKWQ/NwRVM0jVg3/gseDciwl2Wke7R665+/dpVGOIqJpe60ew2ec3VEVWdVqmBoI+XP5zGV4FFPz3X+iTkQn/xdILGc8/thtUYs1jXPfXd/KKKapzho6tOCd8uBxM1GqcmP1IK7QTw8MunCUNfy5B9e2QRdYk9c624M67ikhafX076rkHghZGgwfIyZ3j5QO8djA4e3W/ZtvTrSqFSME7+GxuSrIcYwohZeqP1E6Ih1jWcYyFrM5jYDoW1SLVb8+Z9PitPvkcD3FrGl+InXZACNVu5ay+vgPmeexhLiIXLvoPTY2lLJZ4LVZYsFwtX4lpnGDkn297FMevQxp8Lm2N0yLSVOIj6tARxO5MqAa4kmmpEWee+tVU77nE4s9akQtAqR3FA5+PE+oIcI8NINaDZwRnZk8E5zm1g4JS3BN467lAAOZ5RQwSNy22sIzivrgg1sTRQOQ3jZ2C5fB+qtnNxjHnVHNo7uqXWuQe+d8fpnBb13Pq/p3KjHTH7HTeUYuoCahbG6J4H/Tu+kh7F81o64vSRZ+EsDqX8e6kzS23wNHD X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: aaaaa159-24aa-43b9-e347-08d98fb4fbbe X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 08:22:53.2151 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gjeqKcrQZjDitbBy4TjCGPFty8Pt5VytFAEYttJbUCoFHKql5dtiXOxDSVAzE2SQdMQvI5BmgbTV+B0fZ/320A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5750 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add devicetree binding documentation for amphion Video Processing Unit IP presents on NXP i.MX8Q Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng Reviewed-by: Rob Herring --- .../bindings/media/amphion,vpu.yaml | 180 ++++++++++++++++++ 1 file changed, 180 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/amphion,vpu.yaml diff --git a/Documentation/devicetree/bindings/media/amphion,vpu.yaml b/Documentation/devicetree/bindings/media/amphion,vpu.yaml new file mode 100644 index 000000000000..a9d80eaeeeb6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/amphion,vpu.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amphion,vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amphion VPU codec IP + +maintainers: + - Ming Qian + - Shijie Qin + +description: |- + The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present + on NXP i.MX8Q SoCs. + +properties: + $nodename: + pattern: "^vpu@[0-9a-f]+$" + + compatible: + items: + - enum: + - nxp,imx8qm-vpu + - nxp,imx8qxp-vpu + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^mailbox@[0-9a-f]+$": + description: + Each vpu encoder or decoder correspond a MU, which used for communication + between driver and firmware. Implement via mailbox on driver. + $ref: ../mailbox/fsl,mu.yaml# + + + "^vpu_core@[0-9a-f]+$": + description: + Each core correspond a decoder or encoder, need to configure them + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC + has one decoder and one encoder. + type: object + + properties: + compatible: + items: + - enum: + - nxp,imx8q-vpu-decoder + - nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + items: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + maxItems: 3 + + memory-region: + description: + Phandle to the reserved memory nodes to be associated with the + remoteproc device. The reserved memory nodes should be carveout nodes, + and should be defined as per the bindings in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + items: + - description: region reserved for firmware image sections. + - description: region used for RPC shared memory between firmware and + driver. + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - memory-region + + additionalProperties: false + +required: + - compatible + - reg + - power-domains + +additionalProperties: false + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_core@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + }; + + vpu_core1: vpu_core@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + }; + + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + }; + }; + +...