From patchwork Tue Aug 20 11:24:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 11103583 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5AE21912 for ; Tue, 20 Aug 2019 11:25:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3A00622DA8 for ; Tue, 20 Aug 2019 11:25:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1566300305; bh=C0kicoq9tih86PmzdpH4j+5B+jEevIsiDRDL1K42ByQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=l9TeYrj92oWQs1qOCVoGELe0ztzHMZXCt/4ty5qjB1rRKLGPYBo74SOoH8UprY93R lNgeXDD1aHMVSBtdSOuy02qWtwOHia5cm4SpF+FPanrcVYv3+kwmaY8fwA0BiZsGGZ E8FzRfQfIR07dACPBjjBNS/qZ8k8T3k4cDNDUNlI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729812AbfHTLYw (ORCPT ); Tue, 20 Aug 2019 07:24:52 -0400 Received: from mail.kernel.org ([198.145.29.99]:40864 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729789AbfHTLYu (ORCPT ); Tue, 20 Aug 2019 07:24:50 -0400 Received: from localhost (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 147AE22CF5; Tue, 20 Aug 2019 11:24:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1566300289; bh=C0kicoq9tih86PmzdpH4j+5B+jEevIsiDRDL1K42ByQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GKdugnYKSmp8IN8FmnZ/823whBvDEOcIhYEm/Kg2HmCQm3j2C7YjDvG9FRmm9l0+N Ax1smkgY0Fc8Pu9uvrviIa1g1zZryv/zTvy9gaohxXEKtwI7DHwUOaUGcwdxzInOC1 5WYK4Tvl0buC1Gu4Zs+5LPWok/X15ZYsd4JqhK04= From: Maxime Ripard To: Hans Verkuil , Sakari Ailus , Mauro Carvalho Chehab Cc: Thomas Petazzoni , Laurent Pinchart , linux-media@vger.kernel.org, Chen-Yu Tsai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Mark Rutland , Rob Herring , Frank Rowand , Maxime Ripard Subject: [PATCH v7 4/5] ARM: dts: sun7i: Add CSI0 controller Date: Tue, 20 Aug 2019 13:24:35 +0200 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Maxime Ripard The CSI controller embedded in the A20 can be supported by our new driver. Let's add it to our DT. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 9ad8e445b240..713c20be8c7a 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -376,6 +376,17 @@ num-cs = <1>; }; + csi0: csi@1c09000 { + compatible = "allwinner,sun7i-a20-csi0"; + reg = <0x01c09000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>, + <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "mod", "isp", "ram"; + resets = <&ccu RST_CSI0>; + status = "disabled"; + }; + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; @@ -775,6 +786,20 @@ }; /omit-if-no-ref/ + csi0_8bits_pins: csi-8bits-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi0_clk_pin: csi-clk-pin { + pins = "PE1"; + function = "csi0"; + }; + + /omit-if-no-ref/ emac_pa_pins: emac-pa-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6",