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Tue, 29 Jun 2021 08:22:31 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 12/13] firmware: imx: scu-pd: imx8q: add vpu mu resources Date: Tue, 29 Jun 2021 16:21:13 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: SG2PR06CA0160.apcprd06.prod.outlook.com (2603:1096:1:1e::14) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR06CA0160.apcprd06.prod.outlook.com (2603:1096:1:1e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aE2gC3Nni9T/nISKRN7/PezRYcfwQqf4AjyGOajB55eG9ZwUdqVhAhA/JbPeHiNoDKSF/Ojx5xiX12cmbFkWPxHSdg6Q1pMEJ0h4LObnt3bX6qPvobFQ8jPbgJ6tp8mb6Ee9PNT8fYkERnK9Y5sUR7gYxOJsoRdwVi3YP/ZHACkIJ9JG8n1XxM5qI/tS/8/6jV97wZD5sl4oXk/lhJgtADvki1CJQ956RvNyBlA+yAizzbrKHkPWkZ7e8AFdCZg9OR3azf9lNVmJxDxfoHKZCKb384vp1juoKK9b4KrCxzNsHVTsYp04mFhCqsFttnoLl31dyNmgJzLXbdeRfXPDYdUZftREkS3kvkKyHL4cHh5OLnF8jL/pnV4uo5vxSdql1akFzxJTu6SnqlhFxx4HOg0jsBCxFge9qHJdJSe0MEEpGvLNW7zCl8nEmtjOqFJGuClbZirV8AUKOZUj/EOaSOXuO0YfALfkHQSyIheCM0u/Oob+WWFLTY6Npuh6cTdLezg8X562ysguWJSz1rcpdh26X83qlFFlcrkTooUR8Rw/xJjxjV9KSgNYfaBzbsxakUzLu0xam16iP6uDenqt+iBR1sngCe09Kn9YCiWDvlwl8etXKxHtOyhDS43nJ4lXUZ2KvpJIbLaM5HhKtb/qki8tu2jHinrRvCslSdEd4ndyXPOobdtplXrPKu46dj6fsxyV17o9kO7A93UA+ayxjW+DWJwMYYpMXEo3d8+3DMDwCDXBS0UHYaq9pTLLc6d9NABi3eAjq38eaF1CZNCLuBS21RH2WmdvHcKqmRiSGtQCHl/1b6ZjFNtdmRLX9gB3YcCRtn7+D4uVox4uZQ+FOodnk6/7fxAkY+UHEWQt9TAERRML9xz4xcQkGKZgsuKt06Pas1vZBiw8Uzaerdnc7FPwg8kySBRIODX4lcJE4M9Q3qQcXXzwTR119e+zdydIaL+m+8/q1kUKXabi1lGgr2imX4xNIzUvtCWt49PhwaCK7ZbWftQ71GoU/a0TkSjKUR9BLSiH90ATnXHqXfeeqBsHNme+Po1SRayaPRhZ5i5uTibeIYMgMLDUlzlsHf20YM4XSMWXjJ+95WE3syv8UCbyw0Qu6kPOaifxcR0ObTB8Kb9zRffznadlOROogetyuotC0tmSYF2LwHennKBC+99nXxEg1tvvPUWVmC8q6XafheM1yS5XvKAd65xjrZTCRiYz2ooOicvRvUv7rou0R3BrwN5lKFS3bYEb9N/9GaepAXRIzftuNszgjCWlwEbjEgyJt+pXpbx1ntmYjZF77s60nIF7yk4ObsityqaR2hWsKSIGuue5rF0j9el1BY5d X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1cb4b3de-c87e-41b1-27d1-08d93ad7082c X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2021 08:22:28.2235 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gwPQ9yrxI3AwWrqPQutHrxj2bwLNhMff+gMMpl6yEEwn3jeZjJblrt1Ke2nmfXxcD177C4SW5M+nELc5we0HnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR04MB3089 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org the vpu core depends on the mu resources. if they're missed, the vpu can't work. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index af3d6d9ead28..48bcc9355a7c 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -145,6 +145,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },