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Wed, 02 Sep 2020 19:23:26 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Sep 2020 20:23:24 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 3 Sep 2020 11:23:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 3 Sep 2020 11:23:23 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Stephen Boyd , Nicolas Boichat Subject: [PATCH v3 0/9] Mediatek MT8192 clock support Date: Thu, 3 Sep 2020 11:22:51 +0800 Message-ID: <1599103380-4155-1-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200902_232335_766786_786D49CA X-CRM114-Status: GOOD ( 13.13 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Wendell Lin , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org This series is based on v5.9-rc1 and MT8192 dts[1]. [1] https://patchwork.kernel.org/cover/11713555/ changes since v2: - update and split dt-binding documents by functionalities - add error checking in probe() function - fix incorrect clock relation and add critical clocks - update license identifier and minor fix of coding style changes since v1: - fix asymmetrical control of PLL - have en_mask used as divider enable mask on all MediaTek SoC Weiyi Lu (9): dt-bindings: ARM: Mediatek: Document bindings for MT8192 BSP dt-bindings: ARM: Mediatek: Document bindings for MT8192 Audio dt-bindings: ARM: Mediatek: Document bindings for MT8192 Multimedia dt-bindings: ARM: Mediatek: Document bindings for MT8192 Camera dt-bindings: ARM: Mediatek: Document bindings for MT8192 APU and GPU clk: mediatek: Add dt-bindings for MT8192 clocks clk: mediatek: Fix asymmetrical PLL enable and disable control clk: mediatek: Add configurable enable control to mtk_pll_data clk: mediatek: Add MT8192 clock support .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../arm/mediatek/mediatek,camsys-raw.yaml | 54 + .../bindings/arm/mediatek/mediatek,camsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 2 + .../arm/mediatek/mediatek,imp_iic_wrap.yaml | 78 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,ipesys.txt | 1 + .../arm/mediatek/mediatek,mdpsys.yaml | 38 + .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../bindings/arm/mediatek/mediatek,msdc.yaml | 46 + .../arm/mediatek/mediatek,pericfg.yaml | 1 + .../arm/mediatek/mediatek,scp-adsp.yaml | 38 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vdecsys-soc.yaml | 38 + .../arm/mediatek/mediatek,vdecsys.txt | 1 + .../arm/mediatek/mediatek,vencsys.txt | 1 + drivers/clk/mediatek/Kconfig | 146 ++ drivers/clk/mediatek/Makefile | 24 + drivers/clk/mediatek/clk-mt2701.c | 26 +- drivers/clk/mediatek/clk-mt2712.c | 30 +- drivers/clk/mediatek/clk-mt6765.c | 20 +- drivers/clk/mediatek/clk-mt6779.c | 24 +- drivers/clk/mediatek/clk-mt6797.c | 20 +- drivers/clk/mediatek/clk-mt7622.c | 18 +- drivers/clk/mediatek/clk-mt7629.c | 12 +- drivers/clk/mediatek/clk-mt8173.c | 28 +- drivers/clk/mediatek/clk-mt8183.c | 22 +- drivers/clk/mediatek/clk-mt8192-aud.c | 118 ++ drivers/clk/mediatek/clk-mt8192-cam.c | 72 + drivers/clk/mediatek/clk-mt8192-cam_rawa.c | 59 + drivers/clk/mediatek/clk-mt8192-cam_rawb.c | 59 + drivers/clk/mediatek/clk-mt8192-cam_rawc.c | 59 + drivers/clk/mediatek/clk-mt8192-img.c | 60 + drivers/clk/mediatek/clk-mt8192-img2.c | 62 + .../clk/mediatek/clk-mt8192-imp_iic_wrap_c.c | 61 + .../clk/mediatek/clk-mt8192-imp_iic_wrap_e.c | 58 + .../clk/mediatek/clk-mt8192-imp_iic_wrap_n.c | 59 + .../clk/mediatek/clk-mt8192-imp_iic_wrap_s.c | 60 + .../clk/mediatek/clk-mt8192-imp_iic_wrap_w.c | 58 + .../clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c | 60 + drivers/clk/mediatek/clk-mt8192-ipe.c | 64 + drivers/clk/mediatek/clk-mt8192-mdp.c | 89 ++ drivers/clk/mediatek/clk-mt8192-mfg.c | 57 + drivers/clk/mediatek/clk-mt8192-mm.c | 108 ++ drivers/clk/mediatek/clk-mt8192-msdc.c | 57 + drivers/clk/mediatek/clk-mt8192-msdc_top.c | 71 + drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 57 + drivers/clk/mediatek/clk-mt8192-vdec.c | 82 + drivers/clk/mediatek/clk-mt8192-vdec_soc.c | 82 + drivers/clk/mediatek/clk-mt8192-venc.c | 60 + drivers/clk/mediatek/clk-mt8192.c | 1340 +++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 2 + drivers/clk/mediatek/clk-mux.h | 15 + drivers/clk/mediatek/clk-pll.c | 28 +- include/dt-bindings/clock/mt8192-clk.h | 592 ++++++++ 57 files changed, 4116 insertions(+), 108 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawa.c create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawb.c create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawc.c create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c create mode 100644 drivers/clk/mediatek/clk-mt8192-img2.c create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c create mode 100644 drivers/clk/mediatek/clk-mt8192-mdp.c create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc.c create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc_top.c create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec_soc.c create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c create mode 100644 drivers/clk/mediatek/clk-mt8192.c create mode 100644 include/dt-bindings/clock/mt8192-clk.h