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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:28:25 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 00/13] Mediatek MT6735 main clock and reset drivers Date: Wed, 4 May 2022 16:25:48 +0400 Message-Id: <20220504122601.335495-1-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_052827_638897_DE593A9F X-CRM114-Status: GOOD ( 14.49 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana This series adds support for the main clock and reset controllers on the Mediatek MT6735 SoC: - apmixedsys (global PLLs) - topckgen (global divisors and muxes) - infracfg (gates and resets for internal components) - pericfg (gates and resets for peripherals) MT6735 has other more specialized clock controllers, support for which is not included in this series: - imgsys (camera) - mmsys (display) - vdecsys (video decoder) - audsys (audio) Some symbols in common objects are exported to get the drivers to compile as modules, and mtk_unregister_reset_controller() is implemented to allow for unregistering reset controllers in the infracfg and pericfg drivers when unloading them. Yassine Oudjana (13): dt-bindings: clock: Add Mediatek MT6735 clock bindings dt-bindings: reset: Add MT6735 reset bindings dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles clk: composite: Export clk_unregister_composite clk: mediatek: Export mtk_free_clk_data clk: mediatek: Add driver for MT6735 apmixedsys clk: mediatek: Add driver for MT6735 topckgen clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: reset: Export mtk_register_reset_controller symbols clk: mediatek: reset: Return mtk_reset pointer on register clk: mediatek: reset: Implement mtk_unregister_reset_controller() API clk: mediatek: Add driver for MT6735 infracfg clk: mediatek: Add driver for MT6735 pericfg .../arm/mediatek/mediatek,infracfg.yaml | 8 +- .../arm/mediatek/mediatek,pericfg.yaml | 1 + .../bindings/clock/mediatek,apmixedsys.yaml | 4 +- .../bindings/clock/mediatek,topckgen.yaml | 4 +- MAINTAINERS | 16 + drivers/clk/clk-composite.c | 1 + drivers/clk/mediatek/Kconfig | 28 + drivers/clk/mediatek/Makefile | 4 + drivers/clk/mediatek/clk-gate.c | 1 + drivers/clk/mediatek/clk-mt6735-apmixed.c | 274 ++++ drivers/clk/mediatek/clk-mt6735-infracfg.c | 265 ++++ drivers/clk/mediatek/clk-mt6735-pericfg.c | 360 +++++ drivers/clk/mediatek/clk-mt6735-topckgen.c | 1159 +++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 1 + drivers/clk/mediatek/clk-mtk.h | 8 +- drivers/clk/mediatek/reset.c | 31 +- .../clock/mediatek,mt6735-apmixedsys.h | 16 + .../clock/mediatek,mt6735-infracfg.h | 25 + .../clock/mediatek,mt6735-pericfg.h | 37 + .../clock/mediatek,mt6735-topckgen.h | 79 ++ .../reset/mediatek,mt6735-infracfg.h | 31 + .../reset/mediatek,mt6735-pericfg.h | 31 + 22 files changed, 2366 insertions(+), 18 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixed.c create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h