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Wed, 09 Oct 2024 05:02:15 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 9 Oct 2024 20:02:09 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 9 Oct 2024 20:02:08 +0800 From: Andy-ld Lu To: , , , , , CC: , , , , , Andy-ld Lu Subject: [PATCH v3 0/3] Add mtk-sd support for MT8196 Date: Wed, 9 Oct 2024 20:01:23 +0800 Message-ID: <20241009120203.14913-1-andy-ld.lu@mediatek.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.718400-8.000000 X-TMASE-MatchedRID: 6Pyq8tKkRyftt0HEL3BUV7iMC5wdwKqdLoYOuiLW+uXfq/+cvg1NCKip 18v0DWYVnxamL54dKNbAFycL8Ymu1rhhaFskSWDqYwaJXrf2IXSL6a+kPOEFsJ6fSoF3Lt+MMqR wky9xOk45imXDx6zyYOFr39PS7zaEgZI1n6aNUzbJ5W6OZe5hhYEcpMn6x9cZOW8XgChxVdgwfX HHXt4W1FoqhwIvssPy3c3CRAd2bOE2UEKHDN0wzBlckvO1m+JcTJDl9FKHbrmdohxAwFG9tKPFj JEFr+olwXCBO/GKkVqOhzOa6g8KraTORqtbRsP2nTRjrsQn0THUTvWJ9mbf13z4B5fjDcKL3YG1 Y8RuI/JK31unxphxzudGiGOk5aHhKyVJb/VK9KDdknd0aVk9DuLDq7G+Ik/yv22xKJRyIGVDnOx ozmpp1r+WvXJiKHRLKUZy1dpMKy4= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.718400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 02CD6116B37BFC20CAFB3C4A291E803122577B9430CD7D288F9F17C22E29986A2000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_050218_178322_566306E6 X-CRM114-Status: GOOD ( 12.53 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org There are some new features for Mediatek SoC MT8196, which include new command/data transmitting and receiving path (abbreviated as tx/rx), and two modified register settings. The driver code has to be adapted to implement the above changes, and the compatible string 'mediatek,mt8196-mmc' is added to driver and devicetree bindings. --- Changes in v3: - Separate the settings for stop_dly_sel and pop_en_cnt to a different commit; - Add the original value of stop_dly_sel to the platdata of legacy SoCs, for unified code setting; - Change to return if host->top_base is NULL in msdc_new_tx_setting function, to simplify coding; - Optimize the location of assignment for 'timing_changed' in msdc_set_mclk function. Changes in v2: - Use compatible string 'mediatek,mt8196-mmc' to replace 'mediatek,msdc-v2'; - Remove the 'mediatek,stop-dly-sel', 'mediatek,pop-en-cnt' and 'mediatek, prohibit-gate-cg' in devicetree bindings, due to SoC dependent; - Add 'stop_dly_sel' and 'pop_en_cnt' to the compatiblity structure for different register settings; - The SoC's upgraded version would discard the bus design that detect source clock CG when the CPU access the IP registers, so drop the related control flow with 'prohibit_gate_cg' flag. Link to v1: https://patchwork.kernel.org/patch/13812924 --- Andy-ld Lu (3): mmc: mtk-sd: Add support for MT8196 mmc: mtk-sd: Add two settings in platdata dt-bindings: mmc: mtk-sd: Add support for MT8196 .../devicetree/bindings/mmc/mtk-sd.yaml | 2 + drivers/mmc/host/mtk-sd.c | 166 +++++++++++++++--- 2 files changed, 147 insertions(+), 21 deletions(-)