Message ID | 20250213080008.2984807-1-quic_ziqichen@quicinc.com (mailing list archive) |
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Thu, 13 Feb 2025 08:00:20 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 51D80KW9020786; Thu, 13 Feb 2025 08:00:20 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 51D80J5n020784 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:20 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 393357) id E17CE40C04; Thu, 13 Feb 2025 16:00:18 +0800 (CST) From: Ziqi Chen <quic_ziqichen@quicinc.com> To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, quic_ziqichen@quicinc.com, quic_nguyenb@quicinc.com, quic_nitirawa@quicinc.com, peter.wang@mediatek.com, quic_rampraka@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, Neil Armstrong <neil.armstrong@linaro.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support:Keyword:mediatek), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support:Keyword:mediatek), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support:Keyword:mediatek) Subject: [PATCH v5 0/8] Support Multi-frequency scale for UFS Date: Thu, 13 Feb 2025 16:00:00 +0800 Message-Id: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; 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Series | Support Multi-frequency scale for UFS | expand |
Ziqi, > With OPP V2 enabled, devfreq can scale clocks amongst multiple > frequency plans. However, the gear speed is only toggled between min > and max during clock scaling. Enable multi-level gear scaling by > mapping clock frequencies to gear speeds, so that when devfreq scales > clock frequencies we can put the UFS link at the appropraite gear > speeds accordingly. Applied to 6.15/scsi-staging, thanks!