From patchwork Mon Apr 20 09:25:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "pi-cheng.chen" X-Patchwork-Id: 6241181 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 392929F1BE for ; Mon, 20 Apr 2015 09:26:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 176AA20304 for ; Mon, 20 Apr 2015 09:26:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF6B420303 for ; Mon, 20 Apr 2015 09:26:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yk7yQ-00039o-AA; Mon, 20 Apr 2015 09:26:38 +0000 Received: from mail-pd0-f182.google.com ([209.85.192.182]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yk7y8-00031C-GB for linux-mediatek@lists.infradead.org; Mon, 20 Apr 2015 09:26:21 +0000 Received: by pdbnk13 with SMTP id nk13so202125854pdb.0 for ; Mon, 20 Apr 2015 02:25:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=IxvQRR6crtCxDRuDAxaSVvB6sbrLJ1bphmfYTm+wlBQ=; b=m2Twr8919RvujR1cVIHwA1T4+hOPXZp48ljY/XWyMxCTsk/GDHrVDObp/+2XmCj4Im 4Nzn0aj86zA1TZ16AWEO3DBqnpHOTh7OBHj5x2g63Ham8NEEtD5GYJbMuHX4JqJIHtcA HIVjwFiiQb/pzC4el9AUkQlFYaU7TSsui9/WoNI03Iy8gNHdVlcMrmB/y+Q/D1C4KSPj 3yYP7RBTaeTMq+VNXQAkQLWin4sUHInPuHZiDwmmQ4wQEAxeGJXv5iKhZvGBVymdBojy ovy2xTfMJu9b5XueXEPaftZcKU7rnMn9Bb1A/R2j7yhrjmw+u9onsI//+YGyBg+bXHPU KK4w== X-Gm-Message-State: ALoCoQnwXr43nJr+DiWYxlnMX8HtKBo9GvNi9Tn55cGONqgkZY237OFFL5ytuHA7kpUl4/sB+Vh7 X-Received: by 10.70.103.10 with SMTP id fs10mr26136801pdb.141.1429521958345; Mon, 20 Apr 2015 02:25:58 -0700 (PDT) Received: from phil-BU401LG.mediatek.inc ([124.219.30.17]) by mx.google.com with ESMTPSA id qm2sm6736808pdb.57.2015.04.20.02.25.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Apr 2015 02:25:57 -0700 (PDT) From: "pi-cheng.chen" To: Mike Turquette , Stephen Boyd , Matthias Brugger , Sascha Hauer Subject: [PATCH v2] clk: mediatek: Export CPU mux clocks for CPU frequency control Date: Mon, 20 Apr 2015 17:25:50 +0800 Message-Id: <1429521950-16431-1-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150420_022620_649447_AB25EB70 X-CRM114-Status: GOOD ( 19.29 ) X-Spam-Score: -1.4 (-) Cc: James Liao , linaro-kernel@lists.linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Henry Chen , fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, "Joe.C" , Eddie Huang , "pi-cheng.chen" , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds CPU mux clocks which are used by Mediatek cpufreq driver for intermediate clock source switching. It is based on v11 of common clock support for Mediatek MT8135 and MT8173[1] [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-April/335967.html Changes in v2: - Remove use of .determine_rate callback Signed-off-by: pi-cheng.chen --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-cpumux.c | 122 +++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-cpumux.h | 31 +++++++++ drivers/clk/mediatek/clk-mt8173.c | 23 +++++++ include/dt-bindings/clock/mt8173-clk.h | 4 +- 5 files changed, 180 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/mediatek/clk-cpumux.c create mode 100644 drivers/clk/mediatek/clk-cpumux.h diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 8e4b2a4..299917a 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,4 +1,4 @@ -obj-y += clk-mtk.o clk-pll.o clk-gate.o +obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-cpumux.o obj-$(CONFIG_RESET_CONTROLLER) += reset.o obj-y += clk-mt8135.o obj-y += clk-mt8173.o diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c new file mode 100644 index 0000000..dc14074 --- /dev/null +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015 Linaro Ltd. + * Author: Pi-Cheng Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-cpumux.h" + +static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw) +{ + return container_of(_hw, struct mtk_clk_cpumux, hw); +} + +static u8 clk_cpumux_get_parent(struct clk_hw *hw) +{ + struct mtk_clk_cpumux *mux = to_clk_mux(hw); + int num_parents = __clk_get_num_parents(hw->clk); + u32 val; + + regmap_read(mux->regmap, mux->reg, &val); + + val >>= mux->shift; + val &= mux->mask; + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index) +{ + struct mtk_clk_cpumux *mux = to_clk_mux(hw); + u32 mask, val; + + val = index << mux->shift; + mask = mux->mask << mux->shift; + + return regmap_update_bits(mux->regmap, mux->reg, mask, val); +} + +static struct clk_ops clk_cpumux_ops = { + .get_parent = clk_cpumux_get_parent, + .set_parent = clk_cpumux_set_parent, +}; + +static struct clk *mtk_clk_register_cpumux(const struct mtk_composite *mux, + struct regmap *regmap) +{ + struct mtk_clk_cpumux *cpumux; + struct clk *clk; + struct clk_init_data init; + + cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL); + if (!cpumux) + return ERR_PTR(-ENOMEM); + + init.name = mux->name; + init.ops = &clk_cpumux_ops; + init.parent_names = mux->parent_names; + init.num_parents = mux->num_parents; + + cpumux->reg = mux->mux_reg; + cpumux->shift = mux->mux_shift; + cpumux->mask = (BIT(mux->mux_width) - 1); + cpumux->regmap = regmap; + cpumux->hw.init = &init; + + clk = clk_register(NULL, &cpumux->hw); + if (IS_ERR(clk)) + kfree(cpumux); + + return clk; +} + +int mtk_clk_register_cpumuxes(struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data) +{ + int i; + struct clk *clk; + struct regmap *regmap; + + if (!clk_data) + return -ENOMEM; + + regmap = syscon_node_to_regmap(node); + if (IS_ERR(regmap)) { + pr_err("Cannot find regmap for %s: %ld\n", node->full_name, + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + for (i = 0; i < num; i++) { + const struct mtk_composite *mux = &clks[i]; + + clk = mtk_clk_register_cpumux(mux, regmap); + if (IS_ERR(clk)) { + pr_err("Failed to register clk %s: %ld\n", + mux->name, PTR_ERR(clk)); + continue; + } + + clk_data->clks[mux->id] = clk; + } + + return 0; +} diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h new file mode 100644 index 0000000..b82ad20 --- /dev/null +++ b/drivers/clk/mediatek/clk-cpumux.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015 Linaro Ltd. + * Author: Pi-Cheng Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRV_CLK_CPUMUX_H +#define __DRV_CLK_CPUMUX_H + +#include + +struct mtk_clk_cpumux { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; + u8 shift; +}; + +int mtk_clk_register_cpumuxes(struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data); +#endif /* __DRV_CLK_CPUMUX_H */ diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 0584554..745f9d9 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -19,6 +19,7 @@ #include "clk-mtk.h" #include "clk-gate.h" +#include "clk-cpumux.h" #include @@ -517,6 +518,20 @@ static const char * const i2s3_b_ck_parents[] __initconst = { "apll2_div5" }; +static const char * const ca53_parents[] __initconst = { + "clk26m", + "armca7pll", + "mainpll", + "univpll" +}; + +static const char * const ca57_parents[] __initconst = { + "clk26m", + "armca15pll", + "mainpll", + "univpll" +}; + static const struct mtk_composite top_muxes[] __initconst = { /* CLK_CFG_0 */ MUX(TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), @@ -589,6 +604,11 @@ static const struct mtk_composite top_muxes[] __initconst = { MUX(TOP_I2S3_B_CK_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), }; +static const struct mtk_composite cpu_muxes[] __initconst = { + MUX(INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), + MUX(INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2), +}; + static void __init mtk_init_clk_topckgen(void __iomem *top_base, struct clk_onecell_data *clk_data) { @@ -745,6 +765,9 @@ static void __init mtk_infrasys_init(struct device_node *node) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index e648b28..2503b03 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -187,7 +187,9 @@ #define INFRA_CEC 9 #define INFRA_PMICSPI 10 #define INFRA_PMICWRAP 11 -#define INFRA_NR_CLK 12 +#define INFRA_CA53SEL 12 +#define INFRA_CA57SEL 13 +#define INFRA_NR_CLK 14 /* PERI_SYS */