From patchwork Tue Jun 30 07:02:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mars Cheng X-Patchwork-Id: 6694321 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3F7DEC05AC for ; Tue, 30 Jun 2015 07:04:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3D07E2055B for ; Tue, 30 Jun 2015 07:04:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 381DF2055A for ; Tue, 30 Jun 2015 07:04:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z9pak-00014Q-PR; Tue, 30 Jun 2015 07:04:26 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z9paX-0000mO-1f; Tue, 30 Jun 2015 07:04:14 +0000 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1540253537; Tue, 30 Jun 2015 15:03:49 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Tue, 30 Jun 2015 15:03:47 +0800 From: Mars Cheng To: Matthias Brugger Subject: [PATCH v2 2/2] ARM: dts: mediatek: add 6580 support Date: Tue, 30 Jun 2015 15:02:31 +0800 Message-ID: <1435647751-20422-3-git-send-email-mars.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1435647751-20422-1-git-send-email-mars.cheng@mediatek.com> References: <1435647751-20422-1-git-send-email-mars.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150630_000413_502061_D1F1E15B X-CRM114-Status: GOOD ( 19.48 ) X-Spam-Score: -1.1 (-) Cc: scott.shu@mediatek.com, cc.hwang@mediatek.com, Mars Cheng , linux-kernel@vger.kernel.org, jades.shih@mediatek.com, srv_wsdupstream@mediatek.com, miles.chen@mediatek.com, linux-mediatek@lists.infradead.org, my.chung@mediatek.com, yingjoe.chen@mediatek.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds basic chip support for Mediatek 6580. Change-Id: Ic5c93eb5d1e6e23503dabd28d41c30a7f02e9c18 Signed-off-by: Mars Cheng --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/mt6580-evbp1.dts | 35 +++++++++++ arch/arm/boot/dts/mt6580.dtsi | 125 +++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 arch/arm/boot/dts/mt6580-evbp1.dts create mode 100644 arch/arm/boot/dts/mt6580.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 86217db..9298531 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -656,6 +656,7 @@ dtb-$(CONFIG_MACH_DOVE) += \ dove-d3plug.dtb \ dove-dove-db.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6580-evbp1.dtb \ mt6589-aquaris5.dtb \ mt6592-evb.dtb \ mt8127-moose.dtb \ diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mt6580-evbp1.dts new file mode 100644 index 0000000..8c42335 --- /dev/null +++ b/arch/arm/boot/dts/mt6580-evbp1.dts @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt6580.dtsi" + +/ { + model = "MediaTek MT6580 evaluation board"; + compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; + + chosen { + bootargs = "console=ttyS0,921600n8 earlyprintk"; + stdout-path = &uart0; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi new file mode 100644 index 0000000..ac97d64 --- /dev/null +++ b/arch/arm/boot/dts/mt6580.dtsi @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt6580"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt6580-timer", + "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6580-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11005000 { + compatible = "mediatek,mt6580-uart", + "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; + + uart1: serial@11006000 { + compatible = "mediatek,mt6580-uart", + "mediatek,mt6577-uart"; + reg = <0x11006000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; +};