From patchwork Mon Jul 6 10:01:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "pi-cheng.chen" X-Patchwork-Id: 6721511 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 09B93C05AC for ; Mon, 6 Jul 2015 10:01:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C4B3420712 for ; Mon, 6 Jul 2015 10:01:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B397E206F9 for ; Mon, 6 Jul 2015 10:01:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZC3Dk-0006DG-FU; Mon, 06 Jul 2015 10:01:52 +0000 Received: from mail-pd0-f180.google.com ([209.85.192.180]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZC3Dd-00068B-26 for linux-mediatek@lists.infradead.org; Mon, 06 Jul 2015 10:01:45 +0000 Received: by pddu5 with SMTP id u5so15950715pdd.3 for ; Mon, 06 Jul 2015 03:01:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+HXbUzQjg00qojv/9hv+SGmK3d1JowI9r4Az3q6u+78=; b=mzPE5bFUacrvqV63KHjqDQKGksYH6oBsOP50JptZFFkT9aGwWBHtKKjD3d7eXrh9uo wVX4A3PNpusqbwjU9ENXfNUPJDVy8MMrX7yUhgxIZ0jjl4t77Hj6m7RXTCzrU8v5jfgB 57B7G+dGAxnDrYH9ljmdDGeJKqCCNsvCIni1AfTeT8+jYCfcCF0BiTA2AEJdKEBPWTwH Da71qPBUQpzVyHsTvx2xDHh72T2v/uWchdbsH5XFtEI8m0uopFAhSG+o6lmJzdTsMJ2p N1vc/mXA3W/Tlvlf6pZak6bJitJrmvAnagmFaNo3t7SK8o034tZKjPHEsDlCCYiU/TTw DwAw== X-Gm-Message-State: ALoCoQkULYrZeFMgHGYrgcB6xW/LCCKWPrs2HT+UNvYDiFsMY2c5M8uV6UTTEQv7pZcXmNSzj05U X-Received: by 10.70.3.98 with SMTP id b2mr97078809pdb.107.1436176883697; Mon, 06 Jul 2015 03:01:23 -0700 (PDT) Received: from localhost.localdomain ([124.219.30.17]) by mx.google.com with ESMTPSA id pj6sm17703163pac.18.2015.07.06.03.01.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Jul 2015 03:01:22 -0700 (PDT) From: Pi-Cheng Chen To: Michael Turquette , Stephen Boyd , Sascha Hauer , Matthias Brugger , James Liao Subject: [PATCH v3] clk: mediatek: Export CPU mux clocks for CPU frequency control Date: Mon, 6 Jul 2015 18:01:14 +0800 Message-Id: <1436176874-5729-1-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150706_030145_159952_8D4E4636 X-CRM114-Status: GOOD ( 22.01 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, "pi-cheng.chen" , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "pi-cheng.chen" This patch adds CPU mux clocks which are used by Mediatek cpufreq driver for intermediate clock source switching. Changes in v3: - Rebase to 4.2-rc1 - Fix some issues of v2 Changes in v2: - Remove use of .determine_rate callback Signed-off-by: Pi-Cheng Chen Reviewed-by: Daniel Kurtz --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-cpumux.c | 119 +++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-cpumux.h | 30 +++++++++ drivers/clk/mediatek/clk-mt8173.c | 23 +++++++ include/dt-bindings/clock/mt8173-clk.h | 4 +- 5 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/mediatek/clk-cpumux.c create mode 100644 drivers/clk/mediatek/clk-cpumux.h diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 8e4b2a4..299917a 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,4 +1,4 @@ -obj-y += clk-mtk.o clk-pll.o clk-gate.o +obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-cpumux.o obj-$(CONFIG_RESET_CONTROLLER) += reset.o obj-y += clk-mt8135.o obj-y += clk-mt8173.o diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c new file mode 100644 index 0000000..593df45 --- /dev/null +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2015 Linaro Ltd. + * Author: Pi-Cheng Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-cpumux.h" + +static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw) +{ + return container_of(_hw, struct mtk_clk_cpumux, hw); +} + +static u8 clk_cpumux_get_parent(struct clk_hw *hw) +{ + struct mtk_clk_cpumux *mux = to_clk_mux(hw); + int num_parents = __clk_get_num_parents(hw->clk); + unsigned int val; + + regmap_read(mux->regmap, mux->reg, &val); + + val >>= mux->shift; + val &= mux->mask; + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index) +{ + struct mtk_clk_cpumux *mux = to_clk_mux(hw); + u32 mask, val; + + val = index << mux->shift; + mask = mux->mask << mux->shift; + + return regmap_update_bits(mux->regmap, mux->reg, mask, val); +} + +static const struct clk_ops clk_cpumux_ops = { + .get_parent = clk_cpumux_get_parent, + .set_parent = clk_cpumux_set_parent, +}; + +static struct clk *mtk_clk_register_cpumux(const struct mtk_composite *mux, + struct regmap *regmap) +{ + struct mtk_clk_cpumux *cpumux; + struct clk *clk; + struct clk_init_data init; + + cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL); + if (!cpumux) + return ERR_PTR(-ENOMEM); + + init.name = mux->name; + init.ops = &clk_cpumux_ops; + init.parent_names = mux->parent_names; + init.num_parents = mux->num_parents; + init.flags = mux->flags; + + cpumux->reg = mux->mux_reg; + cpumux->shift = mux->mux_shift; + cpumux->mask = BIT(mux->mux_width) - 1; + cpumux->regmap = regmap; + cpumux->hw.init = &init; + + clk = clk_register(NULL, &cpumux->hw); + if (IS_ERR(clk)) + kfree(cpumux); + + return clk; +} + +int mtk_clk_register_cpumuxes(struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data) +{ + int i; + struct clk *clk; + struct regmap *regmap; + + regmap = syscon_node_to_regmap(node); + if (IS_ERR(regmap)) { + pr_err("Cannot find regmap for %s: %d\n", node->full_name, + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + for (i = 0; i < num; i++) { + const struct mtk_composite *mux = &clks[i]; + + clk = mtk_clk_register_cpumux(mux, regmap); + if (IS_ERR(clk)) { + pr_err("Failed to register clk %s: %ld\n", + mux->name, PTR_ERR(clk)); + continue; + } + + clk_data->clks[mux->id] = clk; + } + + return 0; +} diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h new file mode 100644 index 0000000..dddaad5 --- /dev/null +++ b/drivers/clk/mediatek/clk-cpumux.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015 Linaro Ltd. + * Author: Pi-Cheng Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRV_CLK_CPUMUX_H +#define __DRV_CLK_CPUMUX_H + +struct mtk_clk_cpumux { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; + u8 shift; +}; + +int mtk_clk_register_cpumuxes(struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data); + +#endif /* __DRV_CLK_CPUMUX_H */ diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 4b9e04c..d14183b 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -19,6 +19,7 @@ #include "clk-mtk.h" #include "clk-gate.h" +#include "clk-cpumux.h" #include @@ -517,6 +518,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = { "apll2_div5" }; +static const char * const ca53_parents[] __initconst = { + "clk26m", + "armca7pll", + "mainpll", + "univpll" +}; + +static const char * const ca57_parents[] __initconst = { + "clk26m", + "armca15pll", + "mainpll", + "univpll" +}; + +static struct mtk_composite cpu_muxes[] __initdata = { + MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), + MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2), +}; + static const struct mtk_composite top_muxes[] __initconst = { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), @@ -738,6 +758,9 @@ static void __init mtk_infrasys_init(struct device_node *node) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 4ad76ed..5501cec 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -187,7 +187,9 @@ #define CLK_INFRA_CEC 9 #define CLK_INFRA_PMICSPI 10 #define CLK_INFRA_PMICWRAP 11 -#define CLK_INFRA_NR_CLK 12 +#define CLK_INFRA_CA53SEL 12 +#define CLK_INFRA_CA57SEL 13 +#define CLK_INFRA_NR_CLK 14 /* PERI_SYS */