From patchwork Thu Aug 20 09:19:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leilk Liu X-Patchwork-Id: 7042751 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 357AEC05AC for ; Thu, 20 Aug 2015 09:20:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5E70E205B6 for ; Thu, 20 Aug 2015 09:20:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85DAB205AA for ; Thu, 20 Aug 2015 09:20:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZSM1d-0005ly-83; Thu, 20 Aug 2015 09:20:45 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZSM1a-0005P5-8h; Thu, 20 Aug 2015 09:20:42 +0000 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1893039255; Thu, 20 Aug 2015 17:20:19 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Thu, 20 Aug 2015 17:20:17 +0800 From: Leilk Liu To: Mark Brown Subject: [PATCH v2 3/4] spi: mediatek: use BIT() to instead of SPI_CMD_*_OFFSET Date: Thu, 20 Aug 2015 17:19:08 +0800 Message-ID: <1440062349-25513-4-git-send-email-leilk.liu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1440062349-25513-1-git-send-email-leilk.liu@mediatek.com> References: <1440062349-25513-1-git-send-email-leilk.liu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150820_022042_558804_DC5C46CF X-CRM114-Status: GOOD ( 15.81 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Leilk Liu , Sascha Hauer , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch removes SPI_CMD_*_OFFSET defines, and uses the BIT(x) defines instead. Signed-off-by: Leilk Liu --- drivers/spi/spi-mt65xx.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 4fa4332..43c1dd5 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -48,15 +48,8 @@ #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 -#define SPI_CMD_ACT_OFFSET 0 -#define SPI_CMD_RESUME_OFFSET 1 -#define SPI_CMD_CPHA_OFFSET 8 -#define SPI_CMD_CPOL_OFFSET 9 -#define SPI_CMD_TXMSBF_OFFSET 12 -#define SPI_CMD_RXMSBF_OFFSET 13 -#define SPI_CMD_RX_ENDIAN_OFFSET 14 -#define SPI_CMD_TX_ENDIAN_OFFSET 15 - +#define SPI_CMD_ACT BIT(0) +#define SPI_CMD_RESUME BIT(1) #define SPI_CMD_RST BIT(2) #define SPI_CMD_PAUSE_EN BIT(4) #define SPI_CMD_DEASSERT BIT(5) @@ -143,9 +136,14 @@ static void mtk_spi_config(struct mtk_spi *mdata, reg_val = readl(mdata->base + SPI_CMD_REG); /* set the mlsbx and mlsbtx */ - reg_val &= ~(SPI_CMD_TXMSBF | SPI_CMD_RXMSBF); - reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET); - reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET); + if (chip_config->tx_mlsb) + reg_val |= SPI_CMD_TXMSBF; + else + reg_val &= ~SPI_CMD_TXMSBF; + if (chip_config->rx_mlsb) + reg_val |= SPI_CMD_RXMSBF; + else + reg_val &= ~SPI_CMD_RXMSBF; /* set the tx/rx endian */ #ifdef __LITTLE_ENDIAN @@ -201,9 +199,14 @@ static int mtk_spi_prepare_message(struct spi_master *master, cpol = spi->mode & SPI_CPOL ? 1 : 0; reg_val = readl(mdata->base + SPI_CMD_REG); - reg_val &= ~(SPI_CMD_CPHA | SPI_CMD_CPOL); - reg_val |= (cpha << SPI_CMD_CPHA_OFFSET); - reg_val |= (cpol << SPI_CMD_CPOL_OFFSET); + if (cpha) + reg_val |= SPI_CMD_CPHA; + else + reg_val &= ~SPI_CMD_CPHA; + if (cpol) + reg_val |= SPI_CMD_CPOL; + else + reg_val &= ~SPI_CMD_CPOL; writel(reg_val, mdata->base + SPI_CMD_REG); chip_config = spi->controller_data; @@ -282,9 +285,9 @@ static void mtk_spi_enable_transfer(struct spi_master *master) cmd = readl(mdata->base + SPI_CMD_REG); if (mdata->state == MTK_SPI_IDLE) - cmd |= 1 << SPI_CMD_ACT_OFFSET; + cmd |= SPI_CMD_ACT; else - cmd |= 1 << SPI_CMD_RESUME_OFFSET; + cmd |= SPI_CMD_RESUME; writel(cmd, mdata->base + SPI_CMD_REG); }