@@ -25,26 +25,31 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt6580-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
+ clock-frequency = <1700000000>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
+ clock-frequency = <1700000000>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
+ clock-frequency = <1700000000>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
+ clock-frequency = <1700000000>;
};
};
@@ -67,6 +72,21 @@
#clock-cells = <0>;
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <13000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
scpsys: scpsys@10006000 {
#power-domain-cells = <1>;
compatible = "mediatek,mt6580-scpsys";
Add arch timer node to enable arch-timer support. MT6580 firmware doesn't correctly setup arch-timer frequency and CNTVOFF, add properties to workaround this. This set cpu enable-method to enable SMP. Signed-off-by: Scott Shu <scott.shu@mediatek.com> --- arch/arm/boot/dts/mt6580.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)