new file mode 100644
@@ -0,0 +1,117 @@
+Mediatek HDMI Encoder
+=====================
+
+The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+its parallel input.
+
+Required properties:
+- compatible: Should be "mediatek,<chip>-hdmi".
+- reg: Physical base address and length of the controller's registers
+- reg-names: must contain "grl", "cec", and "sys".
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "cec", "hdmi_sel", "hdmi_div1", "hdmi_div2",
+ "hdmi_div3", "hdmi_pixel", "hdmi_pll", "aud_bclk", and "aud_spdif".
+- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
+- phys: phandle link to the HDMI PHY node.
+ See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
+- phy-names: must contain "hdmi"
+- ports: A node containing input and output port nodes with endpoint
+ definitions as documented in Documentation/devicetree/bindings/graph.txt.
+- port@0: The input port in the ports node should be connected to a DPI output
+ port.
+
+Optional properties:
+- port@1: The output port in the ports node can be connected to the input port
+ of an attached bridge chip, such as a SlimPort transmitter.
+
+HDMI DDC
+========
+
+The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+- compatible: Should be "mediatek,<chip>-hdmi-ddc"
+- reg: Physical base address and length of the controller's registers
+- clocks: device clock
+- clock-names: Must contain "ddc-i2c".
+
+HDMI PHY
+========
+
+The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+output and drives the HDMI pads.
+
+Required properties:
+- compatible: "mediatek,<chip>-hdmi-phy"
+- reg: Physical base address and length of the module's registers
+- #phy-cells: must be <0>.
+
+Optional properties:
+- ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
+- ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+
+Example:
+
+hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ ibias = <0xa>;
+ ibias_up = <0x1c>;
+ #phy-cells = <0>;
+};
+
+hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0 0x11012000 0 0x1c>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+};
+
+hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>, /* GRL */
+ <0 0x10013000 0 0xbc>, /* CEC */
+ <0 0x14000900 0 0x8>; /* SYS */
+ reg-names = "grl", "cec", "sys";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>,
+ <&topckgen CLK_TOP_HDMI_SEL>,
+ <&topckgen CLK_TOP_HDMITX_DIG_CTS>,
+ <&topckgen CLK_TOP_HDMITXPLL_D2>,
+ <&topckgen CLK_TOP_HDMITXPLL_D3>,
+ <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLLCK>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "cec",
+ "hdmi_sel",
+ "hdmi_div1",
+ "hdmi_div2",
+ "hdmi_div3",
+ "hdmi_pixel",
+ "hdmi_pll",
+ "aud_bclk",
+ "aud_spdif";
+ ddc-i2c-bus = <&hdmi_ddc0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+ };
+};
Add the device tree binding documentation for Mediatek HDMI, HDMI PHY and HDMI DDC devices. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- .../bindings/drm/mediatek/mediatek,hdmi.txt | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,hdmi.txt