From patchwork Wed Sep 30 15:30:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Zabel X-Patchwork-Id: 7299371 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E11AEBEEA4 for ; Wed, 30 Sep 2015 15:31:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8E167206F3 for ; Wed, 30 Sep 2015 15:31:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC59D206B2 for ; Wed, 30 Sep 2015 15:31:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZhJLQ-00008D-Hr; Wed, 30 Sep 2015 15:31:00 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZhJLN-0008QL-FP for linux-mediatek@lists.infradead.org; Wed, 30 Sep 2015 15:30:59 +0000 Received: from dude.hi.4.pengutronix.de ([10.1.0.7] helo=dude.pengutronix.de.) by metis.ext.pengutronix.de with esmtp (Exim 4.80) (envelope-from ) id 1ZhJKi-00006J-4V; Wed, 30 Sep 2015 17:30:16 +0200 From: Philipp Zabel To: dri-devel@lists.freedesktop.org Subject: [RFC v3 5/7] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding Date: Wed, 30 Sep 2015 17:30:04 +0200 Message-Id: <1443627006-15319-6-git-send-email-p.zabel@pengutronix.de> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1443627006-15319-1-git-send-email-p.zabel@pengutronix.de> References: <1443627006-15319-1-git-send-email-p.zabel@pengutronix.de> X-SA-Exim-Connect-IP: 10.1.0.7 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-mediatek@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150930_083057_745394_DAABFAB4 X-CRM114-Status: GOOD ( 13.62 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Bolle , YT Shen , Jitao Shi , Jie Qiu , Pawel Moll , Ian Campbell , Cawa Cheng , Daniel Stone , CK Hu , Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Kumar Gala , Matthias Brugger , Philipp Zabel , Dave Airlie , kernel@pengutronix.de MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the device tree binding documentation for Mediatek HDMI, HDMI PHY and HDMI DDC devices. Signed-off-by: Philipp Zabel --- .../bindings/drm/mediatek/mediatek,hdmi.txt | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,hdmi.txt diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,hdmi.txt new file mode 100644 index 0000000..96d09bf --- /dev/null +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,hdmi.txt @@ -0,0 +1,117 @@ +Mediatek HDMI Encoder +===================== + +The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from +its parallel input. + +Required properties: +- compatible: Should be "mediatek,-hdmi". +- reg: Physical base address and length of the controller's registers +- reg-names: must contain "grl", "cec", and "sys". +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "cec", "hdmi_sel", "hdmi_div1", "hdmi_div2", + "hdmi_div3", "hdmi_pixel", "hdmi_pll", "aud_bclk", and "aud_spdif". +- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing +- phys: phandle link to the HDMI PHY node. + See Documentation/devicetree/bindings/phy/phy-bindings.txt for details. +- phy-names: must contain "hdmi" +- ports: A node containing input and output port nodes with endpoint + definitions as documented in Documentation/devicetree/bindings/graph.txt. +- port@0: The input port in the ports node should be connected to a DPI output + port. + +Optional properties: +- port@1: The output port in the ports node can be connected to the input port + of an attached bridge chip, such as a SlimPort transmitter. + +HDMI DDC +======== + +The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. +The Mediatek's I2C controller is used to interface with I2C devices. + +Required properties: +- compatible: Should be "mediatek,-hdmi-ddc" +- reg: Physical base address and length of the controller's registers +- clocks: device clock +- clock-names: Must contain "ddc-i2c". + +HDMI PHY +======== + +The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel +output and drives the HDMI pads. + +Required properties: +- compatible: "mediatek,-hdmi-phy" +- reg: Physical base address and length of the module's registers +- #phy-cells: must be <0>. + +Optional properties: +- ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa +- ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c + +Example: + +hdmi_phy: hdmi-phy@10209100 { + compatible = "mediatek,mt8173-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + ibias = <0xa>; + ibias_up = <0x1c>; + #phy-cells = <0>; +}; + +hdmi_ddc0: i2c@11012000 { + compatible = "mediatek,mt8173-hdmi-ddc"; + reg = <0 0x11012000 0 0x1c>; + interrupts = ; + clocks = <&pericfg CLK_PERI_I2C5>; +}; + +hdmi0: hdmi@14025000 { + compatible = "mediatek,mt8173-hdmi"; + reg = <0 0x14025000 0 0x400>, /* GRL */ + <0 0x10013000 0 0xbc>, /* CEC */ + <0 0x14000900 0 0x8>; /* SYS */ + reg-names = "grl", "cec", "sys"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_CEC>, + <&topckgen CLK_TOP_HDMI_SEL>, + <&topckgen CLK_TOP_HDMITX_DIG_CTS>, + <&topckgen CLK_TOP_HDMITXPLL_D2>, + <&topckgen CLK_TOP_HDMITXPLL_D3>, + <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLLCK>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "cec", + "hdmi_sel", + "hdmi_div1", + "hdmi_div2", + "hdmi_div3", + "hdmi_pixel", + "hdmi_pll", + "aud_bclk", + "aud_spdif"; + ddc-i2c-bus = <&hdmi_ddc0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + }; +};