@@ -277,6 +277,11 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
@@ -487,6 +492,18 @@
clock-names = "source", "hclk";
status = "disabled";
};
+
+ thermal: thermal@1100b000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "mediatek,mt8173-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
};
};
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJWTDT9AAoJEPFlmONMx+ez3RMQAKgHbBxQNJGKeINIetHYbKjS
chdOWL5OWtRwgi/vQbwq0b35qdvRhPMS5Ufgipjf4xO1BVSu5EOKWFuzgMQ6wh0r
xdFVe1VR188TcEDgc5YfJNMwiJ/eYreATE7EWF5uufXVVk9TAQLKl6b4o/Si2KtU
4Zy2uGQT6ZkwlMn8R1XDRoy0sSW3mnzs4it43YI/dJXYTw8S/OJlPFkUNT8jSFKU
LyIAhnU/Zux9Ueh4YNmRu/csiwuKI+Wpkbyu6fFb224SOmfE9Nz3hAQTmIIMV/FS
WwZ7V3CKCmh4xG7fRmjUu/naHnmWx6esVvdXPPKwr2qRDNX9ELRhq88R5Cue/wrX
gJgFTch6cBDRuNyAfCk1T29FebR0Y9BCuWLpUXGUj1/Rh+wSj/q7q6wNeKwW9TJ5
hIDdMio0fcR1ahmqIwG1NU3zJXpLNDnimD0MVtz/vfE85qBtahnClC9+4kcN0W3r
I6n0qQ/YxFp/xNJuHiBKRfw15RuTKyJBT6VtI+/lNd8YejPwdtqESrEJhL3yN9JM
bJ5sEZeGSOSi0KCXgC2bUq/aYEiedKhEsT0EoqnuIZu4wxk7/DL5Fb+F8py5gllZ
9haA2ryZYDEGLcZbhb8z0wHJD5MDLNFv5MRQw+TpG3oP75Jj5/Ejp+jjmBV9nBZM
PkyZGMUNPcEmvuXPqTR/
=Lp5z
-----END PGP SIGNATURE-----
commit 54d2d3b91b271f0edba2d8dbdf34eb76e37286c7
Author: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue May 12 09:22:29 2015 +0200
ARM64: dts: mt8173: Add thermal/auxadc device nodes
This adds the thermal controller and auxadc nodes to the Mediatek MT8173
dtsi file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
@@ -277,6 +277,11 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
@@ -487,6 +492,18 @@
clock-names = "source", "hclk";
status = "disabled";
};
+
+ thermal: thermal@1100b000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "mediatek,mt8173-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
};
};