From patchwork Fri Feb 5 09:37:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Liao X-Patchwork-Id: 8233051 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9D9599F1C1 for ; Fri, 5 Feb 2016 09:40:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BF3BF2017E for ; Fri, 5 Feb 2016 09:40:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D96552011E for ; Fri, 5 Feb 2016 09:40:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aRcsA-0005QK-VN; Fri, 05 Feb 2016 09:40:14 +0000 Received: from [210.61.82.184] (helo=mailgw02.hq.mediatek.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aRcq9-0002vv-G5; Fri, 05 Feb 2016 09:38:14 +0000 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.hq.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1176300102; Fri, 05 Feb 2016 17:37:40 +0800 Received: from mtksdtcf04.mediatek.inc (10.21.12.144) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Fri, 5 Feb 2016 17:37:39 +0800 From: James Liao To: Matthias Brugger , Mike Turquette , Stephen Boyd , Rob Herring Subject: [PATCH v6 7/7] clk: mediatek: Enable critical clocks for MT2701 Date: Fri, 5 Feb 2016 17:37:30 +0800 Message-ID: <1454665050-37776-8-git-send-email-jamesjj.liao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454665050-37776-1-git-send-email-jamesjj.liao@mediatek.com> References: <1454665050-37776-1-git-send-email-jamesjj.liao@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160205_013810_015291_63F6896E X-CRM114-Status: GOOD ( 11.71 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Sascha Hauer , srv_heupstream@mediatek.com, James Liao , linux-kernel@vger.kernel.org, Arnd Bergmann , Philipp Zabel , linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, John Crispin Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some system clocks should be turned on by default on MT2701. This patch enable these clocks when related clocks have been registered. Signed-off-by: James Liao --- drivers/clk/mediatek/clk-mt2701.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 01722e0..f7b4d52 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -573,6 +573,21 @@ static const struct mtk_gate top_clks[] __initconst = { GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28), }; +static struct clk_onecell_data *top_clk_data __initdata; +static struct clk_onecell_data *pll_clk_data __initdata; + +static void __init mtk_clk_enable_critical(void) +{ + if (!top_clk_data || !pll_clk_data) + return; + + clk_prepare_enable(pll_clk_data->clks[CLK_APMIXED_ARMPLL]); + clk_prepare_enable(top_clk_data->clks[CLK_TOP_AXI_SEL]); + clk_prepare_enable(top_clk_data->clks[CLK_TOP_MEM_SEL]); + clk_prepare_enable(top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); + clk_prepare_enable(top_clk_data->clks[CLK_TOP_RTC_SEL]); +} + static void __init mtk_topckgen_init(struct device_node *node) { struct clk_onecell_data *clk_data; @@ -585,7 +600,7 @@ static void __init mtk_topckgen_init(struct device_node *node) return; } - clk_data = mtk_alloc_clk_data(CLK_TOP_NR); + top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR); mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data); @@ -606,6 +621,8 @@ static void __init mtk_topckgen_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_clk_enable_critical(); } CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init); @@ -1201,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node) struct clk_onecell_data *clk_data; int r; - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls)); + pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls)); if (!clk_data) return; @@ -1212,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_clk_enable_critical(); } CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys", mtk_apmixedsys_init);