From patchwork Fri Feb 26 14:21:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Crispin X-Patchwork-Id: 8437631 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0638BC0553 for ; Fri, 26 Feb 2016 14:24:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6CC1203A5 for ; Fri, 26 Feb 2016 14:24:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CDD26203A1 for ; Fri, 26 Feb 2016 14:24:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aZJJx-00004v-11; Fri, 26 Feb 2016 14:24:41 +0000 Received: from arrakis.dune.hu ([78.24.191.176]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aZJID-0006nk-AR; Fri, 26 Feb 2016 14:22:56 +0000 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 9CA1A28B414; Fri, 26 Feb 2016 15:22:19 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (p548C9F76.dip0.t-ipconnect.de [84.140.159.118]) by arrakis.dune.hu (Postfix) with ESMTPSA; Fri, 26 Feb 2016 15:22:19 +0100 (CET) From: John Crispin To: "David S. Miller" Subject: [PATCH V2 10/12] net-next: mediatek: add support for mt7623 Date: Fri, 26 Feb 2016 15:21:42 +0100 Message-Id: <1456496504-50429-11-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1456496504-50429-1-git-send-email-blogic@openwrt.org> References: <1456496504-50429-1-git-send-email-blogic@openwrt.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160226_062254_023980_022C33ED X-CRM114-Status: GOOD ( 21.43 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Fred=20Chang=20=28=E5=BC=B5=E5=98=89=E5=AE=8F=29?= , Felix Fietkau , =?UTF-8?q?Steven=20Liu=20=28=E5=8A=89=E4=BA=BA=E8=B1=AA=29?= , netdev@vger.kernel.org, =?UTF-8?q?Carlos=20Huang=20=28=E9=BB=83=E5=A3=AB=E5=BD=B0=29?= , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Matthias Brugger , Michael Lee , linux-arm-kernel@lists.infradead.org, John Crispin MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for SoCs from the mt7623 family. With this generation of SoCs we have seen a change from MIPS to ARM cores. Due to the fact that ARM SoC tend to be a bit more complex than MIPS, we need support for power domains. The code should also run on MT2701, however this has not been tested yet on device. To my understanding only changes to the devicetree are required as irqs and reset gpios have changed. The DMA issues have also been solved on this silicon allowing us to run on pure QDMA without having to bringup the PDMA engine. However, in order for QDMA to work, we need to bringup the 3rd DMA engine called FQ_DMA. This just needs to be setup and is more scratch memory used internally by the SoC. The reason is that this SoC has many new advanced features such as internal SFQ QoS and HW_LRO. for these to work, the SoC needs extra DMA memory to be able to reorganize the packets internally. I have not had time yet to look at these new features in detail. Signed-off-by: John Crispin Signed-off-by: Felix Fietkau Signed-off-by: Michael Lee --- drivers/net/ethernet/mediatek/soc_mt7623.c | 169 ++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 drivers/net/ethernet/mediatek/soc_mt7623.c diff --git a/drivers/net/ethernet/mediatek/soc_mt7623.c b/drivers/net/ethernet/mediatek/soc_mt7623.c new file mode 100644 index 0000000..cff9868 --- /dev/null +++ b/drivers/net/ethernet/mediatek/soc_mt7623.c @@ -0,0 +1,169 @@ +/* This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2009-2016 John Crispin + * Copyright (C) 2009-2016 Felix Fietkau + * Copyright (C) 2013-2016 Michael Lee + */ + +#include +#include +#include +#include + +#include "mtk_eth_soc.h" +#include "gsw_mt7620.h" +#include "mdio.h" + +#define MT7620_CDMA_CSG_CFG 0x400 +#define MT7621_CDMP_IG_CTRL (MT7620_CDMA_CSG_CFG + 0x00) +#define MT7621_CDMP_EG_CTRL (MT7620_CDMA_CSG_CFG + 0x04) +#define MT7621_RESET_FE BIT(6) +#define MT7621_L4_VALID BIT(24) + +#define MT7621_TX_DMA_UDF BIT(19) + +#define CDMA_ICS_EN BIT(2) +#define CDMA_UCS_EN BIT(1) +#define CDMA_TCS_EN BIT(0) + +#define GDMA_ICS_EN BIT(22) +#define GDMA_TCS_EN BIT(21) +#define GDMA_UCS_EN BIT(20) + +/* frame engine counters */ +#define MT7621_REG_MIB_OFFSET 0x2000 +#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00) +#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400) +#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40) + +#define GSW_REG_GDMA1_MAC_ADRL 0x508 +#define GSW_REG_GDMA1_MAC_ADRH 0x50C + +#define GSW_REG_GDMA2_MAC_ADRL 0x1508 +#define GSW_REG_GDMA2_MAC_ADRH 0x150C + +#define MT7621_MTK_RST_GL 0x04 +#define MT7620_MTK_INT_STATUS2 0x08 + +#define MT7623_RX_BT_32DWORDS (3 << 11) + +#define MT7621_MTK_GDM1_AF BIT(28) +#define MT7621_MTK_GDM2_AF BIT(29) + +static const u16 mt7623_reg_table[MTK_REG_COUNT] = { + [MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, + [MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, + [MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, + [MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, + [MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, + [MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, + [MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0, + [MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, + [MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, + [MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, + [MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0, + [MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE, + [MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS, + [MTK_REG_MTK_DMA_VID_BASE] = 0, + [MTK_REG_MTK_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT, + [MTK_REG_MTK_RST_GL] = MT7621_MTK_RST_GL, + [MTK_REG_MTK_INT_STATUS2] = MT7620_MTK_INT_STATUS2, +}; + +static void mt7623_mtk_reset(struct mtk_eth *eth) +{ + mtk_reset(eth, MT7621_RESET_FE); +} + +static int mt7623_fwd_config(struct mtk_eth *eth) +{ + int i; + + for (i = 0; i < 2; i++) { + u32 val = mtk_r32(eth, MT7621_GDMA_FWD_CFG(i)); + + /* setup the forward port */ + val &= ~0xffff; + if (eth->soc->dma_type == MTK_QDMA) + val |= 0x5555; + + /* Enable RX checksum */ + val |= GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN; + + /* setup the mac dma */ + mtk_w32(eth, val, MT7621_GDMA_FWD_CFG(i)); + } + + /* Enable RX VLan Offloading */ + mtk_w32(eth, 1, MT7621_CDMP_EG_CTRL); + + /* FE int grouping */ + mtk_w32(eth, 0, 0x20); + + return 0; +} + +static void mt7623_set_mac(struct mtk_mac *mac, unsigned char *macaddr) +{ + unsigned long flags; + + spin_lock_irqsave(&mac->hw->page_lock, flags); + if (mac->id == 0) { + mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], + GSW_REG_GDMA1_MAC_ADRH); + mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | + (macaddr[4] << 8) | macaddr[5], + GSW_REG_GDMA1_MAC_ADRL); + } else { + mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], + GSW_REG_GDMA2_MAC_ADRH); + mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | + (macaddr[4] << 8) | macaddr[5], + GSW_REG_GDMA2_MAC_ADRL); + } + spin_unlock_irqrestore(&mac->hw->page_lock, flags); +} + +static struct mtk_soc_data mt7623_data = { + .hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | + NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | + NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | + NETIF_F_IPV6_CSUM, + .dma_type = MTK_QDMA, + .dma_ring_size = 256, + .napi_weight = 64, + .new_stats = 1, + .padding_64b = 1, + .rx_2b_offset = 1, + .rx_sg_dma = 1, + .has_switch = 1, + .mac_count = 2, + .reset_fe = mt7623_mtk_reset, + .set_mac = mt7623_set_mac, + .fwd_config = mt7623_fwd_config, + .switch_init = mtk_gsw_init, + .reg_table = mt7623_reg_table, + .pdma_glo_cfg = MTK_PDMA_SIZE_16DWORDS | MT7623_RX_BT_32DWORDS, + .rx_int = RT5350_RX_DONE_INT, + .tx_int = RT5350_TX_DONE_INT, + .status_int = (MT7621_MTK_GDM1_AF | MT7621_MTK_GDM2_AF), + .checksum_bit = MT7621_L4_VALID, + .has_carrier = mt7620_has_carrier, + .mdio_read = mt7620_mdio_read, + .mdio_write = mt7620_mdio_write, + .mdio_adjust_link = mt7620_mdio_link_adjust, +}; + +const struct of_device_id of_mtk_match[] = { + { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, + {}, +}; + +MODULE_DEVICE_TABLE(of, of_mtk_match);