From patchwork Thu Apr 14 08:11:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Liao X-Patchwork-Id: 8832651 Return-Path: X-Original-To: patchwork-linux-mediatek@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AAABB9F3A0 for ; Thu, 14 Apr 2016 08:22:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A726C20166 for ; Thu, 14 Apr 2016 08:22:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D20B2011B for ; Thu, 14 Apr 2016 08:22:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aqcY5-0000Mr-HA; Thu, 14 Apr 2016 08:22:49 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aqcT0-0002Wo-Hs; Thu, 14 Apr 2016 08:17:40 +0000 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 793852795; Thu, 14 Apr 2016 16:17:08 +0800 Received: from mtksdtcf04.mediatek.inc (10.21.12.144) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Thu, 14 Apr 2016 16:13:21 +0800 From: James Liao To: Matthias Brugger , Mike Turquette , Stephen Boyd , Rob Herring Subject: [PATCH v7 8/9] clk: mediatek: Add config options for MT2701 subsystem clocks Date: Thu, 14 Apr 2016 16:11:53 +0800 Message-ID: <1460621514-65191-9-git-send-email-jamesjj.liao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460621514-65191-1-git-send-email-jamesjj.liao@mediatek.com> References: <1460621514-65191-1-git-send-email-jamesjj.liao@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160414_011735_184298_90930657 X-CRM114-Status: GOOD ( 11.55 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Sascha Hauer , Arnd Bergmann , James Liao , linux-kernel@vger.kernel.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org, Philipp Zabel , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, John Crispin Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MT2701 subsystem clocks are optional and should be enabled only if their subsystem drivers are ready to control these clocks. Signed-off-by: James Liao --- drivers/clk/mediatek/Kconfig | 44 ++++++++++++++++++++++++++++++++++++++- drivers/clk/mediatek/clk-mt2701.c | 36 ++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 1e56000..5aa6204 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -12,7 +12,49 @@ config COMMON_CLK_MT2701 select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK ---help--- - This driver supports Mediatek MT2701 clocks. + This driver supports Mediatek MT2701 basic clocks. + +config COMMON_CLK_MT2701_MMSYS + bool "Clock driver for Mediatek MT2701 mmsys" + depends on COMMON_CLK + select COMMON_CLK_MT2701 + ---help--- + This driver supports Mediatek MT2701 mmsys clocks. + +config COMMON_CLK_MT2701_IMGSYS + bool "Clock driver for Mediatek MT2701 imgsys" + depends on COMMON_CLK + select COMMON_CLK_MT2701 + ---help--- + This driver supports Mediatek MT2701 imgsys clocks. + +config COMMON_CLK_MT2701_VDECSYS + bool "Clock driver for Mediatek MT2701 vdecsys" + depends on COMMON_CLK + select COMMON_CLK_MT2701 + ---help--- + This driver supports Mediatek MT2701 vdecsys clocks. + +config COMMON_CLK_MT2701_HIFSYS + bool "Clock driver for Mediatek MT2701 hifsys" + depends on COMMON_CLK + select COMMON_CLK_MT2701 + ---help--- + This driver supports Mediatek MT2701 hifsys clocks. + +config COMMON_CLK_MT2701_ETHSYS + bool "Clock driver for Mediatek MT2701 ethsys" + depends on COMMON_CLK + select COMMON_CLK_MT2701 + ---help--- + This driver supports Mediatek MT2701 ethsys clocks. + +config COMMON_CLK_MT2701_BDPSYS + bool "Clock driver for Mediatek MT2701 bdpsys" + depends on COMMON_CLK + select COMMON_CLK_MT2701 + ---help--- + This driver supports Mediatek MT2701 bdpsys clocks. config COMMON_CLK_MT8135 bool "Clock driver for Mediatek MT8135" diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 90294e7..68869ff 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -908,6 +908,8 @@ static void __init mtk_pericfg_init(struct device_node *node) } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init); +#ifdef CONFIG_COMMON_CLK_MT2701_MMSYS + static const struct mtk_gate_regs disp0_cg_regs __initconst = { .set_ofs = 0x0104, .clr_ofs = 0x0108, @@ -991,6 +993,10 @@ static void __init mtk_mmsys_init(struct device_node *node) __func__, r); } +#endif /* CONFIG_COMMON_CLK_MT2701_MMSYS */ + +#ifdef CONFIG_COMMON_CLK_MT2701_IMGSYS + static const struct mtk_gate_regs img_cg_regs __initconst = { .set_ofs = 0x0004, .clr_ofs = 0x0008, @@ -1031,6 +1037,10 @@ static void __init mtk_imgsys_init(struct device_node *node) __func__, r); } +#endif /* CONFIG_COMMON_CLK_MT2701_IMGSYS */ + +#ifdef CONFIG_COMMON_CLK_MT2701_VDECSYS + static const struct mtk_gate_regs vdec0_cg_regs __initconst = { .set_ofs = 0x0000, .clr_ofs = 0x0004, @@ -1082,6 +1092,10 @@ static void __init mtk_vdecsys_init(struct device_node *node) __func__, r); } +#endif /* CONFIG_COMMON_CLK_MT2701_VDECSYS */ + +#ifdef CONFIG_COMMON_CLK_MT2701_HIFSYS + static const struct mtk_gate_regs hif_cg_regs __initconst = { .sta_ofs = 0x0008, }; @@ -1121,6 +1135,10 @@ static void __init mtk_hifsys_init(struct device_node *node) mtk_register_reset_controller(node, 1, 0x34); } +#endif /* CONFIG_COMMON_CLK_MT2701_HIFSYS */ + +#ifdef CONFIG_COMMON_CLK_MT2701_ETHSYS + static const struct mtk_gate_regs eth_cg_regs __initconst = { .sta_ofs = 0x0030, }; @@ -1161,6 +1179,10 @@ static void __init mtk_ethsys_init(struct device_node *node) __func__, r); } +#endif /* CONFIG_COMMON_CLK_MT2701_ETHSYS */ + +#ifdef CONFIG_COMMON_CLK_MT2701_BDPSYS + static const struct mtk_gate_regs bdp0_cg_regs __initconst = { .set_ofs = 0x0104, .clr_ofs = 0x0108, @@ -1259,6 +1281,8 @@ static void __init mtk_bdpsys_init(struct device_node *node) __func__, r); } +#endif /* CONFIG_COMMON_CLK_MT2701_BDPSYS */ + #define MT8590_PLL_FMAX (2000 * MHZ) #define CON0_MT8590_RST_BAR BIT(27) @@ -1333,24 +1357,36 @@ CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys", static const struct of_device_id of_clk_match_tbl[] = { { +#ifdef CONFIG_COMMON_CLK_MT2701_MMSYS .compatible = "mediatek,mt2701-mmsys", .data = mtk_mmsys_init, }, { +#endif +#ifdef CONFIG_COMMON_CLK_MT2701_IMGSYS .compatible = "mediatek,mt2701-imgsys", .data = mtk_imgsys_init, }, { +#endif +#ifdef CONFIG_COMMON_CLK_MT2701_VDECSYS .compatible = "mediatek,mt2701-vdecsys", .data = mtk_vdecsys_init, }, { +#endif +#ifdef CONFIG_COMMON_CLK_MT2701_HIFSYS .compatible = "mediatek,mt2701-hifsys", .data = mtk_hifsys_init, }, { +#endif +#ifdef CONFIG_COMMON_CLK_MT2701_ETHSYS .compatible = "mediatek,mt2701-ethsys", .data = mtk_ethsys_init, }, { +#endif +#ifdef CONFIG_COMMON_CLK_MT2701_BDPSYS .compatible = "mediatek,mt2701-bdpsys", .data = mtk_bdpsys_init, }, { +#endif /* sentinel */ } };