diff mbox

[v4,5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701

Message ID 1465379461-14757-6-git-send-email-honghui.zhang@mediatek.com
State New
Headers show

Commit Message

Honghui Zhang June 8, 2016, 9:51 a.m. UTC
From: Honghui Zhang <honghui.zhang@mediatek.com>

Add the dtsi node of iommu and smi for mt2701.

Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

Comments

Joerg Roedel June 21, 2016, 9:41 a.m. UTC | #1
On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
> 
> Add the dtsi node of iommu and smi for mt2701.
> 
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)

Applied the series, except this last patch. It didn't apply cleanly and
I was not sure how to correctly fix that. Can you please resubmit the
patch based on my arm/mediatek branch once I pushed it?

Thanks,

	Joerg
Honghui Zhang June 21, 2016, 9:55 a.m. UTC | #2
On Tue, 2016-06-21 at 11:41 +0200, Joerg Roedel wrote:
> On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> > 
> > Add the dtsi node of iommu and smi for mt2701.
> > 
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 51 insertions(+)
> 
> Applied the series, except this last patch. It didn't apply cleanly and
> I was not sure how to correctly fix that. Can you please resubmit the
> patch based on my arm/mediatek branch once I pushed it?
> 

I will rebase this one later after your push.
Thanks.

> Thanks,
> 
> 	Joerg
>
Joerg Roedel June 21, 2016, 9:57 a.m. UTC | #3
On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
> 
> Add the dtsi node of iommu and smi for mt2701.
> 
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)

Okay, I pushed my arm/mediatek branch to my tree at

	git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git

Please base the patch on that branch and re-send.

Thanks,

	Joerg
Eddie Huang June 22, 2016, 5:45 a.m. UTC | #4
On Tue, 2016-06-21 at 17:57 +0800, Joerg Roedel wrote:
> On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> > 
> > Add the dtsi node of iommu and smi for mt2701.
> > 
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 51 insertions(+)
> 
> Okay, I pushed my arm/mediatek branch to my tree at
> 
> 	git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
> 
> Please base the patch on that branch and re-send.
> 

I think it is better let Mediatek SoC maintainer Matthias to accept dtsi
patch like other drivers. This can avoid dtsi conflict. As I
remember,last time MT8173 IOMMU dtsi patch accepted in iommu tree and
mt8173.dtsi had conflict with arm soc tree at the merge window. Honghui
should resend this patch to Matthias, and elaborate your dependency with
clock and power domain dtsi, then Matthias know the merge sequence. 

Eddie
Thanks
Honghui Zhang June 22, 2016, 7:45 a.m. UTC | #5
On Wed, 2016-06-22 at 13:45 +0800, Eddie Huang wrote:
> On Tue, 2016-06-21 at 17:57 +0800, Joerg Roedel wrote:
> > On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> > > From: Honghui Zhang <honghui.zhang@mediatek.com>
> > > 
> > > Add the dtsi node of iommu and smi for mt2701.
> > > 
> > > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > > ---
> > >  arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 51 insertions(+)
> > 
> > Okay, I pushed my arm/mediatek branch to my tree at
> > 
> > 	git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
> > 
> > Please base the patch on that branch and re-send.
> > 
> 
> I think it is better let Mediatek SoC maintainer Matthias to accept dtsi
> patch like other drivers. This can avoid dtsi conflict. As I
> remember,last time MT8173 IOMMU dtsi patch accepted in iommu tree and
> mt8173.dtsi had conflict with arm soc tree at the merge window. Honghui
> should resend this patch to Matthias, and elaborate your dependency with
> clock and power domain dtsi, then Matthias know the merge sequence. 
> 

Thanks, Eddie.

Hi, Joerg, 
This one is based on CCF "arm: dts: mt2701: Add clock controller device
nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
support v7"[2],
But these two patchset are still being review now.

Do you think it's better that I send this one later after ccf and power
domain patch got merged, and let Matthias take it?


Thanks.
[1] https://patchwork.kernel.org/patch/9109081
[2]
http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html

> Eddie
> Thanks 
> 
>
Joerg Roedel June 22, 2016, 8:31 a.m. UTC | #6
On Wed, Jun 22, 2016 at 03:45:47PM +0800, Honghui Zhang wrote:
> This one is based on CCF "arm: dts: mt2701: Add clock controller device
> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> support v7"[2],
> But these two patchset are still being review now.
> 
> Do you think it's better that I send this one later after ccf and power
> domain patch got merged, and let Matthias take it?

Sure, but the patches I already merged can stay in the tree for now?



	Joerg
Honghui Zhang June 22, 2016, 8:39 a.m. UTC | #7
On Wed, 2016-06-22 at 10:31 +0200, Joerg Roedel wrote:
> On Wed, Jun 22, 2016 at 03:45:47PM +0800, Honghui Zhang wrote:
> > This one is based on CCF "arm: dts: mt2701: Add clock controller device
> > nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> > support v7"[2],
> > But these two patchset are still being review now.
> > 
> > Do you think it's better that I send this one later after ccf and power
> > domain patch got merged, and let Matthias take it?
> 
> Sure, but the patches I already merged can stay in the tree for now?
> 
> 

I think that driver and dtsi could merged separately, I would prefer
those previous patches stay in the tree if it's OK for you.

Thanks.
> 
> 	Joerg
>
Joerg Roedel June 22, 2016, 8:58 a.m. UTC | #8
On Wed, Jun 22, 2016 at 04:39:01PM +0800, Honghui Zhang wrote:
> I think that driver and dtsi could merged separately, I would prefer
> those previous patches stay in the tree if it's OK for you.

Sure, I send them upstream through my tree.


Thanks,

	Joerg
Matthias Brugger July 3, 2016, 6:24 a.m. UTC | #9
On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
>
> Add the dtsi node of iommu and smi for mt2701.
>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
>

Applied,

Thanks.

> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 42d5a37..363de0d 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -16,6 +16,7 @@
>  #include <dt-bindings/power/mt2701-power.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/memory/mt2701-larb-port.h>
>  #include "skeleton64.dtsi"
>  #include "mt2701-pinfunc.h"
>
> @@ -160,6 +161,16 @@
>  		clock-names = "system-clk", "rtc-clk";
>  	};
>
> +	smi_common: smi@1000c000 {
> +		compatible = "mediatek,mt2701-smi-common";
> +		reg = <0 0x1000c000 0 0x1000>;
> +		clocks = <&infracfg CLK_INFRA_SMI>,
> +			 <&mmsys CLK_MM_SMI_COMMON>,
> +			 <&infracfg CLK_INFRA_SMI>;
> +		clock-names = "apb", "smi", "async";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> +	};
> +
>  	sysirq: interrupt-controller@10200100 {
>  		compatible = "mediatek,mt2701-sysirq",
>  			     "mediatek,mt6577-sysirq";
> @@ -169,6 +180,16 @@
>  		reg = <0 0x10200100 0 0x1c>;
>  	};
>
> +	iommu: mmsys_iommu@10205000 {
> +		compatible = "mediatek,mt2701-m4u";
> +		reg = <0 0x10205000 0 0x1000>;
> +		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&infracfg CLK_INFRA_M4U>;
> +		clock-names = "bclk";
> +		mediatek,larbs = <&larb0 &larb1 &larb2>;
> +		#iommu-cells = <1>;
> +	};
> +
>  	apmixedsys: syscon@10209000 {
>  		compatible = "mediatek,mt2701-apmixedsys", "syscon";
>  		reg = <0 0x10209000 0 0x1000>;
> @@ -234,6 +255,16 @@
>  		status = "disabled";
>  	};
>
> +	larb0: larb@14010000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x14010000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		clocks = <&mmsys CLK_MM_SMI_LARB0>,
> +			 <&mmsys CLK_MM_SMI_LARB0>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> +	};
> +
>  	imgsys: syscon@15000000 {
>  		compatible = "mediatek,mt2701-imgsys", "syscon";
>  		reg = <0 0x15000000 0 0x1000>;
> @@ -241,6 +272,16 @@
>  		status = "disabled";
>  	};
>
> +	larb2: larb@15001000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x15001000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		clocks = <&imgsys CLK_IMG_SMI_COMM>,
> +			 <&imgsys CLK_IMG_SMI_COMM>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> +	};
> +
>  	vdecsys: syscon@16000000 {
>  		compatible = "mediatek,mt2701-vdecsys", "syscon";
>  		reg = <0 0x16000000 0 0x1000>;
> @@ -248,6 +289,16 @@
>  		status = "disabled";
>  	};
>
> +	larb1: larb@16010000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x16010000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		clocks = <&vdecsys CLK_VDEC_CKGEN>,
> +			 <&vdecsys CLK_VDEC_LARB>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> +	};
> +
>  	hifsys: syscon@1a000000 {
>  		compatible = "mediatek,mt2701-hifsys", "syscon";
>  		reg = <0 0x1a000000 0 0x1000>;
>
Matthias Brugger July 3, 2016, 7:12 p.m. UTC | #10
On 07/03/2016 08:24 AM, Matthias Brugger wrote:
>
>
> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
>> From: Honghui Zhang <honghui.zhang@mediatek.com>
>>
>> Add the dtsi node of iommu and smi for mt2701.
>>
>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
>> ---
>>  arch/arm/boot/dts/mt2701.dtsi | 51
>> +++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 51 insertions(+)
>>
>
> Applied,

Please resend the patch including the infracfg and mmsys node.

Regards,
Matthias

>
> Thanks.
>
>> diff --git a/arch/arm/boot/dts/mt2701.dtsi
>> b/arch/arm/boot/dts/mt2701.dtsi
>> index 42d5a37..363de0d 100644
>> --- a/arch/arm/boot/dts/mt2701.dtsi
>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>> @@ -16,6 +16,7 @@
>>  #include <dt-bindings/power/mt2701-power.h>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/memory/mt2701-larb-port.h>
>>  #include "skeleton64.dtsi"
>>  #include "mt2701-pinfunc.h"
>>
>> @@ -160,6 +161,16 @@
>>          clock-names = "system-clk", "rtc-clk";
>>      };
>>
>> +    smi_common: smi@1000c000 {
>> +        compatible = "mediatek,mt2701-smi-common";
>> +        reg = <0 0x1000c000 0 0x1000>;
>> +        clocks = <&infracfg CLK_INFRA_SMI>,
>> +             <&mmsys CLK_MM_SMI_COMMON>,
>> +             <&infracfg CLK_INFRA_SMI>;
>> +        clock-names = "apb", "smi", "async";
>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>> +    };
>> +
>>      sysirq: interrupt-controller@10200100 {
>>          compatible = "mediatek,mt2701-sysirq",
>>                   "mediatek,mt6577-sysirq";
>> @@ -169,6 +180,16 @@
>>          reg = <0 0x10200100 0 0x1c>;
>>      };
>>
>> +    iommu: mmsys_iommu@10205000 {
>> +        compatible = "mediatek,mt2701-m4u";
>> +        reg = <0 0x10205000 0 0x1000>;
>> +        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>> +        clocks = <&infracfg CLK_INFRA_M4U>;
>> +        clock-names = "bclk";
>> +        mediatek,larbs = <&larb0 &larb1 &larb2>;
>> +        #iommu-cells = <1>;
>> +    };
>> +
>>      apmixedsys: syscon@10209000 {
>>          compatible = "mediatek,mt2701-apmixedsys", "syscon";
>>          reg = <0 0x10209000 0 0x1000>;
>> @@ -234,6 +255,16 @@
>>          status = "disabled";
>>      };
>>
>> +    larb0: larb@14010000 {
>> +        compatible = "mediatek,mt2701-smi-larb";
>> +        reg = <0 0x14010000 0 0x1000>;
>> +        mediatek,smi = <&smi_common>;
>> +        clocks = <&mmsys CLK_MM_SMI_LARB0>,
>> +             <&mmsys CLK_MM_SMI_LARB0>;
>> +        clock-names = "apb", "smi";
>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>> +    };
>> +
>>      imgsys: syscon@15000000 {
>>          compatible = "mediatek,mt2701-imgsys", "syscon";
>>          reg = <0 0x15000000 0 0x1000>;
>> @@ -241,6 +272,16 @@
>>          status = "disabled";
>>      };
>>
>> +    larb2: larb@15001000 {
>> +        compatible = "mediatek,mt2701-smi-larb";
>> +        reg = <0 0x15001000 0 0x1000>;
>> +        mediatek,smi = <&smi_common>;
>> +        clocks = <&imgsys CLK_IMG_SMI_COMM>,
>> +             <&imgsys CLK_IMG_SMI_COMM>;
>> +        clock-names = "apb", "smi";
>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
>> +    };
>> +
>>      vdecsys: syscon@16000000 {
>>          compatible = "mediatek,mt2701-vdecsys", "syscon";
>>          reg = <0 0x16000000 0 0x1000>;
>> @@ -248,6 +289,16 @@
>>          status = "disabled";
>>      };
>>
>> +    larb1: larb@16010000 {
>> +        compatible = "mediatek,mt2701-smi-larb";
>> +        reg = <0 0x16010000 0 0x1000>;
>> +        mediatek,smi = <&smi_common>;
>> +        clocks = <&vdecsys CLK_VDEC_CKGEN>,
>> +             <&vdecsys CLK_VDEC_LARB>;
>> +        clock-names = "apb", "smi";
>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
>> +    };
>> +
>>      hifsys: syscon@1a000000 {
>>          compatible = "mediatek,mt2701-hifsys", "syscon";
>>          reg = <0 0x1a000000 0 0x1000>;
>>
Honghui Zhang July 4, 2016, 1:32 a.m. UTC | #11
On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
> 
> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
> >
> >
> > On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
> >> From: Honghui Zhang <honghui.zhang@mediatek.com>
> >>
> >> Add the dtsi node of iommu and smi for mt2701.
> >>
> >> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> >> ---
> >>  arch/arm/boot/dts/mt2701.dtsi | 51
> >> +++++++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 51 insertions(+)
> >>
> >
> > Applied,
> 
> Please resend the patch including the infracfg and mmsys node.
> 

Hi, Matthias,

Please hold this one.
This one is based on CCF "arm: dts: mt2701: Add clock controller device
nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
support v7"[2],
But these two patchset are still being reviewed now.

Do you think it's better that I send this one later after ccf and power
domain patch got merged? I will send this patch later if it's OK with
you.

Thanks.
[1] https://patchwork.kernel.org/patch/9109081
[2]
http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html

> Regards,
> Matthias
> 
> >
> > Thanks.
> >
> >> diff --git a/arch/arm/boot/dts/mt2701.dtsi
> >> b/arch/arm/boot/dts/mt2701.dtsi
> >> index 42d5a37..363de0d 100644
> >> --- a/arch/arm/boot/dts/mt2701.dtsi
> >> +++ b/arch/arm/boot/dts/mt2701.dtsi
> >> @@ -16,6 +16,7 @@
> >>  #include <dt-bindings/power/mt2701-power.h>
> >>  #include <dt-bindings/interrupt-controller/irq.h>
> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/memory/mt2701-larb-port.h>
> >>  #include "skeleton64.dtsi"
> >>  #include "mt2701-pinfunc.h"
> >>
> >> @@ -160,6 +161,16 @@
> >>          clock-names = "system-clk", "rtc-clk";
> >>      };
> >>
> >> +    smi_common: smi@1000c000 {
> >> +        compatible = "mediatek,mt2701-smi-common";
> >> +        reg = <0 0x1000c000 0 0x1000>;
> >> +        clocks = <&infracfg CLK_INFRA_SMI>,
> >> +             <&mmsys CLK_MM_SMI_COMMON>,
> >> +             <&infracfg CLK_INFRA_SMI>;
> >> +        clock-names = "apb", "smi", "async";
> >> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >> +    };
> >> +
> >>      sysirq: interrupt-controller@10200100 {
> >>          compatible = "mediatek,mt2701-sysirq",
> >>                   "mediatek,mt6577-sysirq";
> >> @@ -169,6 +180,16 @@
> >>          reg = <0 0x10200100 0 0x1c>;
> >>      };
> >>
> >> +    iommu: mmsys_iommu@10205000 {
> >> +        compatible = "mediatek,mt2701-m4u";
> >> +        reg = <0 0x10205000 0 0x1000>;
> >> +        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> >> +        clocks = <&infracfg CLK_INFRA_M4U>;
> >> +        clock-names = "bclk";
> >> +        mediatek,larbs = <&larb0 &larb1 &larb2>;
> >> +        #iommu-cells = <1>;
> >> +    };
> >> +
> >>      apmixedsys: syscon@10209000 {
> >>          compatible = "mediatek,mt2701-apmixedsys", "syscon";
> >>          reg = <0 0x10209000 0 0x1000>;
> >> @@ -234,6 +255,16 @@
> >>          status = "disabled";
> >>      };
> >>
> >> +    larb0: larb@14010000 {
> >> +        compatible = "mediatek,mt2701-smi-larb";
> >> +        reg = <0 0x14010000 0 0x1000>;
> >> +        mediatek,smi = <&smi_common>;
> >> +        clocks = <&mmsys CLK_MM_SMI_LARB0>,
> >> +             <&mmsys CLK_MM_SMI_LARB0>;
> >> +        clock-names = "apb", "smi";
> >> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >> +    };
> >> +
> >>      imgsys: syscon@15000000 {
> >>          compatible = "mediatek,mt2701-imgsys", "syscon";
> >>          reg = <0 0x15000000 0 0x1000>;
> >> @@ -241,6 +272,16 @@
> >>          status = "disabled";
> >>      };
> >>
> >> +    larb2: larb@15001000 {
> >> +        compatible = "mediatek,mt2701-smi-larb";
> >> +        reg = <0 0x15001000 0 0x1000>;
> >> +        mediatek,smi = <&smi_common>;
> >> +        clocks = <&imgsys CLK_IMG_SMI_COMM>,
> >> +             <&imgsys CLK_IMG_SMI_COMM>;
> >> +        clock-names = "apb", "smi";
> >> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> >> +    };
> >> +
> >>      vdecsys: syscon@16000000 {
> >>          compatible = "mediatek,mt2701-vdecsys", "syscon";
> >>          reg = <0 0x16000000 0 0x1000>;
> >> @@ -248,6 +289,16 @@
> >>          status = "disabled";
> >>      };
> >>
> >> +    larb1: larb@16010000 {
> >> +        compatible = "mediatek,mt2701-smi-larb";
> >> +        reg = <0 0x16010000 0 0x1000>;
> >> +        mediatek,smi = <&smi_common>;
> >> +        clocks = <&vdecsys CLK_VDEC_CKGEN>,
> >> +             <&vdecsys CLK_VDEC_LARB>;
> >> +        clock-names = "apb", "smi";
> >> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> >> +    };
> >> +
> >>      hifsys: syscon@1a000000 {
> >>          compatible = "mediatek,mt2701-hifsys", "syscon";
> >>          reg = <0 0x1a000000 0 0x1000>;
> >>
Matthias Brugger July 4, 2016, 8 a.m. UTC | #12
On 04/07/16 03:32, Honghui Zhang wrote:
> On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
>>
>> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
>>>
>>>
>>> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
>>>> From: Honghui Zhang <honghui.zhang@mediatek.com>
>>>>
>>>> Add the dtsi node of iommu and smi for mt2701.
>>>>
>>>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
>>>> ---
>>>>   arch/arm/boot/dts/mt2701.dtsi | 51
>>>> +++++++++++++++++++++++++++++++++++++++++++
>>>>   1 file changed, 51 insertions(+)
>>>>
>>>
>>> Applied,
>>
>> Please resend the patch including the infracfg and mmsys node.
>>
>
> Hi, Matthias,
>
> Please hold this one.
> This one is based on CCF "arm: dts: mt2701: Add clock controller device
> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> support v7"[2],
> But these two patchset are still being reviewed now.
>
> Do you think it's better that I send this one later after ccf and power
> domain patch got merged? I will send this patch later if it's OK with
> you.
>

Sounds good.

Thanks a lot,
Matthias

> Thanks.
> [1] https://patchwork.kernel.org/patch/9109081
> [2]
> http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
>
>> Regards,
>> Matthias
>>
>>>
>>> Thanks.
>>>
>>>> diff --git a/arch/arm/boot/dts/mt2701.dtsi
>>>> b/arch/arm/boot/dts/mt2701.dtsi
>>>> index 42d5a37..363de0d 100644
>>>> --- a/arch/arm/boot/dts/mt2701.dtsi
>>>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>>>> @@ -16,6 +16,7 @@
>>>>   #include <dt-bindings/power/mt2701-power.h>
>>>>   #include <dt-bindings/interrupt-controller/irq.h>
>>>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +#include <dt-bindings/memory/mt2701-larb-port.h>
>>>>   #include "skeleton64.dtsi"
>>>>   #include "mt2701-pinfunc.h"
>>>>
>>>> @@ -160,6 +161,16 @@
>>>>           clock-names = "system-clk", "rtc-clk";
>>>>       };
>>>>
>>>> +    smi_common: smi@1000c000 {
>>>> +        compatible = "mediatek,mt2701-smi-common";
>>>> +        reg = <0 0x1000c000 0 0x1000>;
>>>> +        clocks = <&infracfg CLK_INFRA_SMI>,
>>>> +             <&mmsys CLK_MM_SMI_COMMON>,
>>>> +             <&infracfg CLK_INFRA_SMI>;
>>>> +        clock-names = "apb", "smi", "async";
>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>> +    };
>>>> +
>>>>       sysirq: interrupt-controller@10200100 {
>>>>           compatible = "mediatek,mt2701-sysirq",
>>>>                    "mediatek,mt6577-sysirq";
>>>> @@ -169,6 +180,16 @@
>>>>           reg = <0 0x10200100 0 0x1c>;
>>>>       };
>>>>
>>>> +    iommu: mmsys_iommu@10205000 {
>>>> +        compatible = "mediatek,mt2701-m4u";
>>>> +        reg = <0 0x10205000 0 0x1000>;
>>>> +        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>>>> +        clocks = <&infracfg CLK_INFRA_M4U>;
>>>> +        clock-names = "bclk";
>>>> +        mediatek,larbs = <&larb0 &larb1 &larb2>;
>>>> +        #iommu-cells = <1>;
>>>> +    };
>>>> +
>>>>       apmixedsys: syscon@10209000 {
>>>>           compatible = "mediatek,mt2701-apmixedsys", "syscon";
>>>>           reg = <0 0x10209000 0 0x1000>;
>>>> @@ -234,6 +255,16 @@
>>>>           status = "disabled";
>>>>       };
>>>>
>>>> +    larb0: larb@14010000 {
>>>> +        compatible = "mediatek,mt2701-smi-larb";
>>>> +        reg = <0 0x14010000 0 0x1000>;
>>>> +        mediatek,smi = <&smi_common>;
>>>> +        clocks = <&mmsys CLK_MM_SMI_LARB0>,
>>>> +             <&mmsys CLK_MM_SMI_LARB0>;
>>>> +        clock-names = "apb", "smi";
>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>> +    };
>>>> +
>>>>       imgsys: syscon@15000000 {
>>>>           compatible = "mediatek,mt2701-imgsys", "syscon";
>>>>           reg = <0 0x15000000 0 0x1000>;
>>>> @@ -241,6 +272,16 @@
>>>>           status = "disabled";
>>>>       };
>>>>
>>>> +    larb2: larb@15001000 {
>>>> +        compatible = "mediatek,mt2701-smi-larb";
>>>> +        reg = <0 0x15001000 0 0x1000>;
>>>> +        mediatek,smi = <&smi_common>;
>>>> +        clocks = <&imgsys CLK_IMG_SMI_COMM>,
>>>> +             <&imgsys CLK_IMG_SMI_COMM>;
>>>> +        clock-names = "apb", "smi";
>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
>>>> +    };
>>>> +
>>>>       vdecsys: syscon@16000000 {
>>>>           compatible = "mediatek,mt2701-vdecsys", "syscon";
>>>>           reg = <0 0x16000000 0 0x1000>;
>>>> @@ -248,6 +289,16 @@
>>>>           status = "disabled";
>>>>       };
>>>>
>>>> +    larb1: larb@16010000 {
>>>> +        compatible = "mediatek,mt2701-smi-larb";
>>>> +        reg = <0 0x16010000 0 0x1000>;
>>>> +        mediatek,smi = <&smi_common>;
>>>> +        clocks = <&vdecsys CLK_VDEC_CKGEN>,
>>>> +             <&vdecsys CLK_VDEC_LARB>;
>>>> +        clock-names = "apb", "smi";
>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
>>>> +    };
>>>> +
>>>>       hifsys: syscon@1a000000 {
>>>>           compatible = "mediatek,mt2701-hifsys", "syscon";
>>>>           reg = <0 0x1a000000 0 0x1000>;
>>>>
>
>
Matthias Brugger Jan. 13, 2017, 2:54 p.m. UTC | #13
On 04/07/16 10:00, Matthias Brugger wrote:
>
>
> On 04/07/16 03:32, Honghui Zhang wrote:
>> On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
>>>
>>> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
>>>>
>>>>
>>>> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
>>>>> From: Honghui Zhang <honghui.zhang@mediatek.com>
>>>>>
>>>>> Add the dtsi node of iommu and smi for mt2701.
>>>>>
>>>>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
>>>>> ---
>>>>>   arch/arm/boot/dts/mt2701.dtsi | 51
>>>>> +++++++++++++++++++++++++++++++++++++++++++
>>>>>   1 file changed, 51 insertions(+)
>>>>>
>>>>
>>>> Applied,
>>>
>>> Please resend the patch including the infracfg and mmsys node.
>>>
>>
>> Hi, Matthias,
>>
>> Please hold this one.
>> This one is based on CCF "arm: dts: mt2701: Add clock controller device
>> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
>> support v7"[2],
>> But these two patchset are still being reviewed now.
>>
>> Do you think it's better that I send this one later after ccf and power
>> domain patch got merged? I will send this patch later if it's OK with
>> you.
>>
>
> Sounds good.

Applied now to v4.10-next/dts32

Thanks.

>
> Thanks a lot,
> Matthias
>
>> Thanks.
>> [1] https://patchwork.kernel.org/patch/9109081
>> [2]
>> http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
>>
>>> Regards,
>>> Matthias
>>>
>>>>
>>>> Thanks.
>>>>
>>>>> diff --git a/arch/arm/boot/dts/mt2701.dtsi
>>>>> b/arch/arm/boot/dts/mt2701.dtsi
>>>>> index 42d5a37..363de0d 100644
>>>>> --- a/arch/arm/boot/dts/mt2701.dtsi
>>>>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>>>>> @@ -16,6 +16,7 @@
>>>>>   #include <dt-bindings/power/mt2701-power.h>
>>>>>   #include <dt-bindings/interrupt-controller/irq.h>
>>>>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>> +#include <dt-bindings/memory/mt2701-larb-port.h>
>>>>>   #include "skeleton64.dtsi"
>>>>>   #include "mt2701-pinfunc.h"
>>>>>
>>>>> @@ -160,6 +161,16 @@
>>>>>           clock-names = "system-clk", "rtc-clk";
>>>>>       };
>>>>>
>>>>> +    smi_common: smi@1000c000 {
>>>>> +        compatible = "mediatek,mt2701-smi-common";
>>>>> +        reg = <0 0x1000c000 0 0x1000>;
>>>>> +        clocks = <&infracfg CLK_INFRA_SMI>,
>>>>> +             <&mmsys CLK_MM_SMI_COMMON>,
>>>>> +             <&infracfg CLK_INFRA_SMI>;
>>>>> +        clock-names = "apb", "smi", "async";
>>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>>> +    };
>>>>> +
>>>>>       sysirq: interrupt-controller@10200100 {
>>>>>           compatible = "mediatek,mt2701-sysirq",
>>>>>                    "mediatek,mt6577-sysirq";
>>>>> @@ -169,6 +180,16 @@
>>>>>           reg = <0 0x10200100 0 0x1c>;
>>>>>       };
>>>>>
>>>>> +    iommu: mmsys_iommu@10205000 {
>>>>> +        compatible = "mediatek,mt2701-m4u";
>>>>> +        reg = <0 0x10205000 0 0x1000>;
>>>>> +        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>>>>> +        clocks = <&infracfg CLK_INFRA_M4U>;
>>>>> +        clock-names = "bclk";
>>>>> +        mediatek,larbs = <&larb0 &larb1 &larb2>;
>>>>> +        #iommu-cells = <1>;
>>>>> +    };
>>>>> +
>>>>>       apmixedsys: syscon@10209000 {
>>>>>           compatible = "mediatek,mt2701-apmixedsys", "syscon";
>>>>>           reg = <0 0x10209000 0 0x1000>;
>>>>> @@ -234,6 +255,16 @@
>>>>>           status = "disabled";
>>>>>       };
>>>>>
>>>>> +    larb0: larb@14010000 {
>>>>> +        compatible = "mediatek,mt2701-smi-larb";
>>>>> +        reg = <0 0x14010000 0 0x1000>;
>>>>> +        mediatek,smi = <&smi_common>;
>>>>> +        clocks = <&mmsys CLK_MM_SMI_LARB0>,
>>>>> +             <&mmsys CLK_MM_SMI_LARB0>;
>>>>> +        clock-names = "apb", "smi";
>>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>>> +    };
>>>>> +
>>>>>       imgsys: syscon@15000000 {
>>>>>           compatible = "mediatek,mt2701-imgsys", "syscon";
>>>>>           reg = <0 0x15000000 0 0x1000>;
>>>>> @@ -241,6 +272,16 @@
>>>>>           status = "disabled";
>>>>>       };
>>>>>
>>>>> +    larb2: larb@15001000 {
>>>>> +        compatible = "mediatek,mt2701-smi-larb";
>>>>> +        reg = <0 0x15001000 0 0x1000>;
>>>>> +        mediatek,smi = <&smi_common>;
>>>>> +        clocks = <&imgsys CLK_IMG_SMI_COMM>,
>>>>> +             <&imgsys CLK_IMG_SMI_COMM>;
>>>>> +        clock-names = "apb", "smi";
>>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
>>>>> +    };
>>>>> +
>>>>>       vdecsys: syscon@16000000 {
>>>>>           compatible = "mediatek,mt2701-vdecsys", "syscon";
>>>>>           reg = <0 0x16000000 0 0x1000>;
>>>>> @@ -248,6 +289,16 @@
>>>>>           status = "disabled";
>>>>>       };
>>>>>
>>>>> +    larb1: larb@16010000 {
>>>>> +        compatible = "mediatek,mt2701-smi-larb";
>>>>> +        reg = <0 0x16010000 0 0x1000>;
>>>>> +        mediatek,smi = <&smi_common>;
>>>>> +        clocks = <&vdecsys CLK_VDEC_CKGEN>,
>>>>> +             <&vdecsys CLK_VDEC_LARB>;
>>>>> +        clock-names = "apb", "smi";
>>>>> +        power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
>>>>> +    };
>>>>> +
>>>>>       hifsys: syscon@1a000000 {
>>>>>           compatible = "mediatek,mt2701-hifsys", "syscon";
>>>>>           reg = <0 0x1a000000 0 0x1000>;
>>>>>
>>
>>
Honghui Zhang Jan. 16, 2017, 2:48 a.m. UTC | #14
On Fri, 2017-01-13 at 15:54 +0100, Matthias Brugger wrote:
> 
> On 04/07/16 10:00, Matthias Brugger wrote:
> >
> >
> > On 04/07/16 03:32, Honghui Zhang wrote:
> >> On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
> >>>
> >>> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
> >>>>
> >>>>
> >>>> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
> >>>>> From: Honghui Zhang <honghui.zhang@mediatek.com>
> >>>>>
> >>>>> Add the dtsi node of iommu and smi for mt2701.
> >>>>>
> >>>>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> >>>>> ---
> >>>>>   arch/arm/boot/dts/mt2701.dtsi | 51
> >>>>> +++++++++++++++++++++++++++++++++++++++++++
> >>>>>   1 file changed, 51 insertions(+)
> >>>>>
> >>>>
> >>>> Applied,
> >>>
> >>> Please resend the patch including the infracfg and mmsys node.
> >>>
> >>
> >> Hi, Matthias,
> >>
> >> Please hold this one.
> >> This one is based on CCF "arm: dts: mt2701: Add clock controller device
> >> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> >> support v7"[2],
> >> But these two patchset are still being reviewed now.
> >>
> >> Do you think it's better that I send this one later after ccf and power
> >> domain patch got merged? I will send this patch later if it's OK with
> >> you.
> >>
> >
> > Sounds good.
> 
> Applied now to v4.10-next/dts32
> 
> Thanks.
> 

Thanks.

> >
> > Thanks a lot,
> > Matthias
> >
> >> Thanks.
> >> [1] https://patchwork.kernel.org/patch/9109081
> >> [2]
> >> http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
> >>
diff mbox

Patch

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..363de0d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -16,6 +16,7 @@ 
 #include <dt-bindings/power/mt2701-power.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
 #include "skeleton64.dtsi"
 #include "mt2701-pinfunc.h"
 
@@ -160,6 +161,16 @@ 
 		clock-names = "system-clk", "rtc-clk";
 	};
 
+	smi_common: smi@1000c000 {
+		compatible = "mediatek,mt2701-smi-common";
+		reg = <0 0x1000c000 0 0x1000>;
+		clocks = <&infracfg CLK_INFRA_SMI>,
+			 <&mmsys CLK_MM_SMI_COMMON>,
+			 <&infracfg CLK_INFRA_SMI>;
+		clock-names = "apb", "smi", "async";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	sysirq: interrupt-controller@10200100 {
 		compatible = "mediatek,mt2701-sysirq",
 			     "mediatek,mt6577-sysirq";
@@ -169,6 +180,16 @@ 
 		reg = <0 0x10200100 0 0x1c>;
 	};
 
+	iommu: mmsys_iommu@10205000 {
+		compatible = "mediatek,mt2701-m4u";
+		reg = <0 0x10205000 0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_M4U>;
+		clock-names = "bclk";
+		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		#iommu-cells = <1>;
+	};
+
 	apmixedsys: syscon@10209000 {
 		compatible = "mediatek,mt2701-apmixedsys", "syscon";
 		reg = <0 0x10209000 0 0x1000>;
@@ -234,6 +255,16 @@ 
 		status = "disabled";
 	};
 
+	larb0: larb@14010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x14010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		clocks = <&mmsys CLK_MM_SMI_LARB0>,
+			 <&mmsys CLK_MM_SMI_LARB0>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	imgsys: syscon@15000000 {
 		compatible = "mediatek,mt2701-imgsys", "syscon";
 		reg = <0 0x15000000 0 0x1000>;
@@ -241,6 +272,16 @@ 
 		status = "disabled";
 	};
 
+	larb2: larb@15001000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x15001000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		clocks = <&imgsys CLK_IMG_SMI_COMM>,
+			 <&imgsys CLK_IMG_SMI_COMM>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+	};
+
 	vdecsys: syscon@16000000 {
 		compatible = "mediatek,mt2701-vdecsys", "syscon";
 		reg = <0 0x16000000 0 0x1000>;
@@ -248,6 +289,16 @@ 
 		status = "disabled";
 	};
 
+	larb1: larb@16010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x16010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		clocks = <&vdecsys CLK_VDEC_CKGEN>,
+			 <&vdecsys CLK_VDEC_LARB>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+	};
+
 	hifsys: syscon@1a000000 {
 		compatible = "mediatek,mt2701-hifsys", "syscon";
 		reg = <0 0x1a000000 0 0x1000>;