From patchwork Wed Jul 20 04:06:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 9238783 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DE36B600CB for ; Wed, 20 Jul 2016 04:06:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D28C42624D for ; Wed, 20 Jul 2016 04:06:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C4A992026B; Wed, 20 Jul 2016 04:06:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 540E42026B for ; Wed, 20 Jul 2016 04:06:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bPimN-0006SM-SY; Wed, 20 Jul 2016 04:06:39 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bPimL-0006Cq-8K; Wed, 20 Jul 2016 04:06:38 +0000 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 815573423; Wed, 20 Jul 2016 12:06:14 +0800 Received: from localhost.localdomain (10.21.14.115) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Wed, 20 Jul 2016 12:06:12 +0800 From: Bibby Hsieh To: Mark Rutland , , , , Subject: [PATCH] arm64: dts: mt8173: add tvdpll and vencpll clocks for 4K support Date: Wed, 20 Jul 2016 12:06:11 +0800 Message-ID: <1468987571-39104-1-git-send-email-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160719_210637_536311_B644F375 X-CRM114-Status: GOOD ( 13.24 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , YH Huang , Lorenzo Pieralisi , Junzhi Zhao , Pawel Moll , Ian Campbell , Catalin Marinas , Sascha Hauer , Will Deacon , "dawei.chien@mediatek.com" , Chunfeng Yun , CK Hu , Rob Herring , Philipp Zabel , Kumar Gala , Matthias Brugger , Yingjoe Chen , Eddie Huang , Bibby Hsieh , Yong Wu Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Junzhi Zhao When the resolution is set to 4k*2k, the hdmi pixel clock will be 250MHz, however, the correct pixel clock should be 297MHz. Fix this error by adding the correct tvdpll clocks. If MT8173 can support 4K, the vencpll clock should be 800MHz. Add the vencpll clocks to support 4K. Signed-off-by: Junzhi Zhao Signed-off-by: Bibby Hsieh --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 78529e4..e79bacf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -690,6 +690,8 @@ compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_VENCPLL>; + clock-names = "vencpll"; #clock-cells = <1>; }; @@ -857,10 +859,22 @@ reg = <0 0x1401d000 0 0x1000>; interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DPI_PIXEL>, + clocks = <&topckgen CLK_TOP_TVDPLL_D2>, + <&topckgen CLK_TOP_TVDPLL_D4>, + <&topckgen CLK_TOP_TVDPLL_D8>, + <&topckgen CLK_TOP_TVDPLL_D16>, + <&topckgen CLK_TOP_DPI0_SEL>, + <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; - clock-names = "pixel", "engine", "pll"; + clock-names = "tvdpll_d2", + "tvdpll_d4", + "tvdpll_d8", + "tvdpll_d16", + "tvdpll_mux", + "pixel", + "engine", + "pll"; status = "disabled"; };