From patchwork Wed Jul 27 08:25:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 9249445 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A6D9F60757 for ; Wed, 27 Jul 2016 08:25:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 971512624C for ; Wed, 27 Jul 2016 08:25:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8AF4D27572; Wed, 27 Jul 2016 08:25:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5847B2624C for ; Wed, 27 Jul 2016 08:25:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bSKA1-0005gW-2G; Wed, 27 Jul 2016 08:25:49 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bSK9y-0005YT-By; Wed, 27 Jul 2016 08:25:47 +0000 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1420372624; Wed, 27 Jul 2016 16:25:18 +0800 Received: from localhost.localdomain (10.21.14.115) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Wed, 27 Jul 2016 16:25:17 +0800 From: Bibby Hsieh To: Mark Rutland , , , , Subject: [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support Date: Wed, 27 Jul 2016 16:25:14 +0800 Message-ID: <1469607914-64831-1-git-send-email-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160727_012546_585849_02303682 X-CRM114-Status: GOOD ( 12.33 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , YH Huang , Lorenzo Pieralisi , Junzhi Zhao , Pawel Moll , Ian Campbell , Catalin Marinas , Sascha Hauer , Will Deacon , "dawei.chien@mediatek.com" , Chunfeng Yun , CK Hu , Rob Herring , Philipp Zabel , Kumar Gala , Matthias Brugger , Yingjoe Chen , Eddie Huang , Bibby Hsieh , Yong Wu Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP If MT8173 can support HDMI 4K resoultion, the VENCPLL should be configured to 800MHZ. We didn't set VENCPLL directly, we set the mm_sel to 400MHz statically in the board device tree. Signed-off-by: Bibby Hsieh --- Changes since v2: - Align the clocks of dpi0 node. Changes since v1: - Do not set the VENCPLL by clk_set_rate at display driver. - Configure the mm_sel to 400MHz statically in the board device tree. --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 78529e4..9c22204 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -690,7 +690,9 @@ compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_MM_SEL>; #clock-cells = <1>; + clock-frequency = <400000000>; }; ovl0: ovl@1400c000 {