From patchwork Mon Sep 26 09:26:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erin Lo X-Patchwork-Id: 9350381 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9D3766077B for ; Mon, 26 Sep 2016 09:27:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DC4428C35 for ; Mon, 26 Sep 2016 09:27:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8224B28C86; Mon, 26 Sep 2016 09:27:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3787828C35 for ; Mon, 26 Sep 2016 09:27:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1boSBo-00075D-Oc; Mon, 26 Sep 2016 09:27:08 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1boSBj-00071F-Hy; Mon, 26 Sep 2016 09:27:04 +0000 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 753494688; Mon, 26 Sep 2016 17:26:43 +0800 Received: from mtkslt209.mediatek.inc (10.21.15.96) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Mon, 26 Sep 2016 17:22:51 +0800 From: Erin Lo To: Matthias Brugger , Mike Turquette , Stephen Boyd , Rob Herring Subject: [PATCH v13 2/4] reset: mediatek: Add MT2701 reset driver Date: Mon, 26 Sep 2016 17:26:29 +0800 Message-ID: <1474881991-17429-3-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1474881991-17429-1-git-send-email-erin.lo@mediatek.com> References: <1474881991-17429-1-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160926_022703_795363_BAD98552 X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Sascha Hauer , Arnd Bergmann , James Liao , Erin Lo , ms.chen@mediatek.com, linux-kernel@vger.kernel.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org, Shunli Wang , Philipp Zabel , robert.chou@mediatek.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunli Wang In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang Signed-off-by: James Liao Signed-off-by: Erin Lo Tested-by: John Crispin Acked-by: Philipp Zabel --- drivers/clk/mediatek/clk-mt2701-hif.c | 6 +++++- drivers/clk/mediatek/clk-mt2701.c | 12 ++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index e2b0039..4c0688f 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -53,8 +53,12 @@ static int mtk_hifsys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 1, 0x34); + + return 0; } static const struct of_device_id of_match_clk_mt2701_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index c225256..b2148b6 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -802,8 +802,12 @@ static int mtk_infrasys_init(struct platform_device *pdev) infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 2, 0x30); + + return 0; } static const struct mtk_gate_regs peri0_cg_regs = { @@ -920,8 +924,12 @@ static int mtk_pericfg_init(struct platform_device *pdev) &lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 2, 0x0); + + return 0; } #define MT8590_PLL_FMAX (2000 * MHZ)