| Message ID | 1478245388-1412-5-git-send-email-erin.lo@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 11/04/2016 08:43 AM, Erin Lo wrote: > We used to use a fixed rate clock for the UARTs. Now that we have clock > support we can associate the correct clocks to the UARTs and drop the > 26MHz fixed rate UART clock. > > Signed-off-by: Erin Lo <erin.lo@mediatek.com> Applied, thanks. > --- > arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++---------- > 1 file changed, 8 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi > index c9a8dbf..7eab6f4 100644 > --- a/arch/arm/boot/dts/mt2701.dtsi > +++ b/arch/arm/boot/dts/mt2701.dtsi > @@ -73,12 +73,6 @@ > #clock-cells = <0>; > }; > > - uart_clk: dummy26m { > - compatible = "fixed-clock"; > - clock-frequency = <26000000>; > - #clock-cells = <0>; > - }; > - > clk26m: oscillator@0 { > compatible = "fixed-clock"; > #clock-cells = <0>; > @@ -186,7 +180,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11002000 0 0x400>; > interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > > @@ -195,7 +190,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11003000 0 0x400>; > interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > > @@ -204,7 +200,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11004000 0 0x400>; > interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > > @@ -213,7 +210,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11005000 0 0x400>; > interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > }; >
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index c9a8dbf..7eab6f4 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -73,12 +73,6 @@ #clock-cells = <0>; }; - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - clk26m: oscillator@0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -186,7 +180,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -195,7 +190,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -204,7 +200,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -213,7 +210,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; };
We used to use a fixed rate clock for the UARTs. Now that we have clock support we can associate the correct clocks to the UARTs and drop the 26MHz fixed rate UART clock. Signed-off-by: Erin Lo <erin.lo@mediatek.com> --- arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-)