| Message ID | 1484215490-7494-3-git-send-email-yong.mao@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
-trimmed cc list (future wise, I suggest you be more careful whom to keep on cc/to) On 12 January 2017 at 11:04, Yong Mao <yong.mao@mediatek.com> wrote: > From: yong mao <yong.mao@mediatek.com> > > Add description for hs200-cmd-int-delay > Add description for hs400-cmd-int-delay > Add description for cmd-resp-sel > > Signed-off-by: Yong Mao <yong.mao@mediatek.com> The changes to DTS bindings should come prior the actual code change using the bindings. Please make this patch 1 instead. Otherwise this looks good to me. Kind regards Uffe > --- > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > index 0120c7f..2dbb3b0 100644 > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > @@ -21,6 +21,9 @@ Optional properties: > - assigned-clocks: PLL of the source clock > - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock > - hs400-ds-delay: HS400 DS delay setting > +- hs200-cmd-int-delay: HS200 command internal delay setting > +- hs400-cmd-int-delay: HS400 command internal delay setting > +- cmd-resp-sel: command response sample selection > > Examples: > mmc0: mmc@11230000 { > @@ -38,4 +41,7 @@ mmc0: mmc@11230000 { > assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; > assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; > hs400-ds-delay = <0x14015>; > + hs200-cmd-int-delay = <26>; > + hs400-cmd-int-delay = <14>; > + cmd-resp-sel = <0>; /* 0: rising, 1: falling */ > }; > -- > 1.7.9.5 >
On Thu, Jan 12, 2017 at 06:04:50PM +0800, Yong Mao wrote: > From: yong mao <yong.mao@mediatek.com> > > Add description for hs200-cmd-int-delay > Add description for hs400-cmd-int-delay > Add description for cmd-resp-sel > > Signed-off-by: Yong Mao <yong.mao@mediatek.com> > --- > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > index 0120c7f..2dbb3b0 100644 > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > @@ -21,6 +21,9 @@ Optional properties: > - assigned-clocks: PLL of the source clock > - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock > - hs400-ds-delay: HS400 DS delay setting > +- hs200-cmd-int-delay: HS200 command internal delay setting > +- hs400-cmd-int-delay: HS400 command internal delay setting What are the units and range of values? These need vendor prefix as well. > +- cmd-resp-sel: command response sample selection Looks like a boolean. State that and make the default the more common case. > > Examples: > mmc0: mmc@11230000 { > @@ -38,4 +41,7 @@ mmc0: mmc@11230000 { > assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; > assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; > hs400-ds-delay = <0x14015>; > + hs200-cmd-int-delay = <26>; > + hs400-cmd-int-delay = <14>; > + cmd-resp-sel = <0>; /* 0: rising, 1: falling */ > }; > -- > 1.7.9.5 >
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 0120c7f..2dbb3b0 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -21,6 +21,9 @@ Optional properties: - assigned-clocks: PLL of the source clock - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock - hs400-ds-delay: HS400 DS delay setting +- hs200-cmd-int-delay: HS200 command internal delay setting +- hs400-cmd-int-delay: HS400 command internal delay setting +- cmd-resp-sel: command response sample selection Examples: mmc0: mmc@11230000 { @@ -38,4 +41,7 @@ mmc0: mmc@11230000 { assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; hs400-ds-delay = <0x14015>; + hs200-cmd-int-delay = <26>; + hs400-cmd-int-delay = <14>; + cmd-resp-sel = <0>; /* 0: rising, 1: falling */ };